# US 12,191,266 B2 · Semiconductor device and manufacturing method of semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,266 B2 - Document ID: US12191266B2 - Status: Granted - Kind: B2 - Application number: 17/692,779 - Filed: 2022-03-11 - Published: 2023-03-23 - Granted: 2025-01-07 - Earliest claimed: 2021-09-21 - Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Applicants: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation - Inventors: Emiko Inoue; Yukie Nishikawa - Web page: https://patentgrep.com/patent/US12191266B2 ## CPC - H10D 64/281: {Base electrodes for bipolar transistors} - H10W 72/90: Bond pads, in general - H10D 12/411: {Insulated-gate bipolar transistors [IGBT]} - H10D 64/518: {characterised by their lengths or sectional shapes} - H10W 72/019: {of bond pads} - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/01953: {by etching} - H10W 72/921: {Structures or relative sizes of bond pads} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9232: {with additional elements interposed between layers} - H10W 72/925: {Bond pads having a filler embedded in a matrix} - H10W 72/934: {Cross-sectional shape, i.e. in side view} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes a silicon substrate, a first layer, a second layer, a barrier metal, and a gate pad. The first layer is formed of an oxide film provided on an upper surface of the silicon substrate. The second layer is a layer at least selectively having a projecting and recessed part on an upper surface of the first layer, the projecting and recessed part having a projection and recess deeper than a projection and recess occurring when the layer is formed in a planar shape. The barrier metal is formed on an upper surface of the second layer according to a shape of the projecting and recessed part. The gate pad is in close contact with the silicon substrate via the barrier metal. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate; a first layer formed of an oxide film provided on an upper surface of the semiconductor substrate; a second layer which is a layer formed on an upper surface of the first layer and at least selectively having a projection and a recess in an upper surface of the second layer, the projection and the recess being deeper than unintentional fine bumps on an upper surface of the second layer, the unintentional fine bumps occurring during manufacturing process for forming the upper surface of the second layer in a planar shape; a barrier metal formed on the upper surface of the second layer according to a shape of the projection and the recess; and a pad in close contact with the second layer via the barrier metal. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, which is an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein: the second layer comprises: polysilicon selectively formed on the upper surface of the first layer; and an interlayer film formed at least in a region where the polysilicon is not formed on the upper surface of the first layer; and the projection and the recess are formed on an upper surface of the polysilicon. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein: the second layer comprises: polysilicon selectively formed on the upper surface of the first layer; and an interlayer film formed at least in a region where the polysilicon is not formed on the upper surface of the first layer; and the projection and the recess are formed of the interlayer film selectively arranged on an upper surface of the polysilicon. ### Claim 5 (depends on 1) The semiconductor device according to claim 1, further comprising a metal plug formed at least on a side wall of a projection and a recess of the barrier metal formed according to the projection and the recess in the upper surface of the second layer, on an upper surface of the barrier metal, wherein the pad is formed on the upper surface of the barrier metal via the plug in at least a partial region. ### Claim 6 (depends on 5) The semiconductor device according to claim 5, wherein: the plug is formed flat by filling the projection and the recess of the barrier metal formed according to the projection and the recess in the upper surface of the second layer; and the pad is formed on the upper surface of the barrier metal via the plug. ### Claim 7 (depends on 1) The semiconductor device according to claim 1, wherein the projection and the recess are formed in a stripe shape, a quadrangular shape, a swirl shape, a check shape, a honeycomb shape or an octagonal shape in plan view. ### Claim 8 (depends on 1) The semiconductor device according to claim 1, wherein a height of each of the unintentional fine bumps is up to about 150 nm. ### Claim 9 (depends on 1) The semiconductor device according to claim 1, wherein the second layer includes a plurality of projections and recesses. ### Claim 10 A semiconductor device comprising: a semiconductor substrate; a first layer formed of an oxide film provided on an upper surface of the semiconductor substrate; a second layer which is on an upper surface of the first layer and has a projection and a recess in an upper surface of the second layer, the projection and the recess comprising the recess being deeper than fine bumps in a first surface surrounding the projection and the recess; a barrier metal formed on the upper surface of the second layer according to a shape of the projection and the recess; and a pad in close contact with the second layer via the barrier metal. ### Claim 11 (depends on 10) The semiconductor device according to claim 10, which is an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). ### Claim 12 (depends on 10) The semiconductor device according to claim 10, wherein: the second layer comprises: polysilicon selectively formed on the upper surface of the first layer; and an interlayer film formed at least in a region where the polysilicon is not formed on the upper surface of the first layer; and the projection and the recess are formed on an upper surface of the polysilicon. ### Claim 13 (depends on 10) The semiconductor device according to claim 10, wherein: the second layer comprises: polysilicon selectively formed on the upper surface of the first layer; and an interlayer film formed at least in a region where the polysilicon is not formed on the upper surface of the first layer; and the projection and the recess are formed of the interlayer film selectively arranged on an upper surface of the polysilicon. ### Claim 14 (depends on 10) The semiconductor device according to claim 10, further comprising a metal plug formed at least on a side wall of a projection and recess of the barrier metal formed according to the projection and the recess in the upper surface of the second layer, on an upper surface of the barrier metal, wherein the pad is formed on the upper surface of the barrier metal via the plug in at least a partial region. ### Claim 15 (depends on 14) The semiconductor device according to claim 14, wherein: the plug is formed flat by filling the projection and recess of the barrier metal formed according to the projection and the recess in the upper surface of the second layer; and the pad is formed on the upper surface of the barrier metal via the plug. ### Claim 16 (depends on 1) The semiconductor device according to claim 1, wherein the projection and the recess are formed in a stripe shape, a quadrangular shape, a swirl shape, a check shape, a honeycomb shape or an octagonal shape in plan view. ### Claim 17 (depends on 10) The semiconductor device according to claim 10, wherein: the second layer comprises a silicon layer. ### Claim 18 (depends on 10) The semiconductor device according to claim 10, wherein: the first surface comprises a plain surface. ### Claim 19 A manufacturing method of a semiconductor device, comprising: forming a first layer being an oxide film, on an upper surface of a semiconductor substrate; forming a second layer on an upper surface of the first layer; forming a mask based on a pattern of a first projection and recess on an upper surface of the second layer; forming the first projection and recess on the second layer by an etching treatment based on the mask; removing the mask; film-forming a barrier metal on the upper surface of the second layer; and film-forming a metal which forms a pad on an upper surface of the barrier metal. ### Claim 20 (depends on 19) The manufacturing method according to claim 19, further comprising film-forming, between the film-forming the barrier metal and the film-forming the metal which forms the pad, a metal different from a metal which forms the barrier metal and the metal which forms the pad, at least on a side wall in a region where the barrier metal formed along the first projection and recess is formed.