# US 12,191,263 B2 · Semiconductor structure and manufacturing method of semiconductor structure

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,191,263 B2
- Document ID: US12191263B2
- Status: Granted
- Kind: B2
- Application number: 17/648,130
- Filed: 2022-01-16
- Published: 2022-09-01
- Granted: 2025-01-07
- Earliest claimed: 2021-03-01
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Mengmeng Wang; Hsin-Pin Huang
- Web page: https://patentgrep.com/patent/US12191263B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 42/00: Arrangements for protection of devices (arrangements for thermal protection H10W40/00)
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/503: {Located in scribe lines}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a chip structure and a sealing structure disposed on a substrate of the semiconductor structure. The sealing structure includes a metal wall body and a blocking wall body located on a top of the metal wall body, and the metal wall body and the blocking wall body both are disposed around the chip structure.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate;
a chip structure and a sealing structure located on the substrate, wherein
the sealing structure comprises a metal wall body and a blocking wall body located on a top of the metal wall body; and
the metal wall body and the blocking wall body both are disposed around the chip structure;
a sealing layer, located on a side of the sealing structure away from the substrate; and
an interlayer dielectric layer and an etching stop layer, wherein the metal wall body and the blocking wall body are located in the interlayer dielectric layer and the etching stop layer, and the sealing layer covers the top surface of the interlayer dielectric layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein a plurality of blocking wall bodies are disposed at intervals around the chip structure.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein the plurality of blocking wall bodies are all located on the top of the metal wall body.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the blocking wall body is integral with the sealing layer.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein a material of the blocking wall body comprises an insulation material.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, further comprising:
a scribe line located between the sealing structures, wherein a top surface of a part of the sealing layer on the blocking wall body is higher than a top surface of a part of the sealing layer on the scribe line.

### Claim 7 (depends on 5)

The semiconductor structure of claim 5, wherein the material of the blocking wall body and a material of the sealing layer both include silicon nitride.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the blocking wall body covers a part of a top surface of the metal wall body.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein the metal wall body comprises a plurality of sub wall bodies sequentially stacked in a direction perpendicular to the substrate, and projections of adjacent sub wall bodies of the plurality of sub wall bodies on the substrate at least partially overlap.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein each of the sub wall bodies is disposed in the same layer as a metal layer in the chip structure.