# US 12,191,258 B2 · Semiconductor device having integral alignment marks with decoupling features and method for fabricating the same

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- Number: US 12,191,258 B2
- Document ID: US12191258B2
- Status: Granted
- Kind: B2
- Application number: 17/541,772
- Filed: 2021-12-03
- Published: 2023-06-08
- Granted: 2025-01-07
- Earliest claimed: 2021-12-03
- Assignees: Nanya Technology Corporation
- Applicants: Nanya Technology Corporation
- Inventors: Shing-Yih Shih
- Web page: https://patentgrep.com/patent/US12191258B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G03F 9/708: {Mark formation}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 46/301: {for alignment}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)

## Abstract

The present application discloses a semiconductor device having integral alignment marks with decoupling features and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a dielectric stack positioned on the substrate; two conductive features positioned in the dielectric stack; a decoupling unit positioned in the dielectric stack, between the two second conductive features, and comprising a bottle-shaped cross-sectional profile; and an alignment mark positioned on the decoupling unit. The alignment mark comprises a fluorescence material.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate;
a dielectric stack positioned on the substrate;
two second conductive features positioned in the dielectric stack;
a decoupling unit positioned in the dielectric stack, between the two second conductive features, wherein the decoupling unit has low dielectric constant for providing decoupling function and for reducing parasitic capacitance of the second conductive features; and
an alignment mark positioned on the decoupling unit;
wherein the alignment mark comprises a fluorescent material; wherein the fluorescent material comprises azobenzene; wherein the decoupling unit comprises a porous low-k material;
wherein the dielectric stack comprises a first dielectric layer positioned on the substrate, a second dielectric layer positioned on the first dielectric layer, a middle dielectric layer positioned on the second dielectric layer, a third dielectric layer positioned on the middle dielectric layer, and a fourth dielectric layer positioned on the third dielectric layer, and the two second conductive features and the decoupling unit are positioned in the middle dielectric layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the alignment mark is positioned along the fourth dielectric layer and the third dielectric layer and positioned on the decoupling unit.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the alignment mark positioned along the fourth dielectric layer and the third dielectric layer and extending to the decoupling unit.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein sidewalls of the alignment mark are tapered.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a width between two valleys of sidewalls of the decoupling unit is greater than a width of a top surface of the alignment mark.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein a width of a top surface of the alignment mark is greater than a width of the alignment mark at an interface between the middle dielectric layer and the third dielectric layer.

### Claim 7 (depends on 4)

The semiconductor device of claim 4, wherein a width of the alignment mark at an interface between the middle dielectric layer and the third dielectric layer is greater than a width of a bottom surface of the alignment mark.

### Claim 8 (depends on 4)

The semiconductor device of claim 4, wherein a width of the alignment mark at an interface between the middle dielectric layer and the third dielectric layer is greater than a width of a bottom surface of the decoupling unit.

### Claim 9 (depends on 4)

The semiconductor device of claim 4, wherein the two second conductive features respectively comprises a bottom barrier layer positioned on the second dielectric layer, a middle conductive layer positioned on the bottom barrier layer, a top barrier layer positioned on the middle conductive layer, and a spacer barrier layer positioned on sidewalls of the bottom barrier layer, the middle conductive layer, and the top barrier layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the bottom barrier layer and the top barrier layer comprise the same material.

### Claim 11 (depends on 1)

The semiconductor device of claim 1, wherein the first dielectric layer and the third dielectric layer comprise the same material.

### Claim 12 (depends on 1)

The semiconductor device of claim 1, wherein the second dielectric layer and the fourth dielectric layer comprise the same material.