# US 12,191,250 B2 · Method of forming bottom electrode via for memory device

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- Number: US 12,191,250 B2
- Document ID: US12191250B2
- Status: Granted
- Kind: B2
- Application number: 17/725,906
- Filed: 2022-04-21
- Published: 2023-07-27
- Granted: 2025-01-07
- Earliest claimed: 2022-01-27
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Zhen Yu Guan; Sheng-Wen Fu; Hsun-Chung Kuang
- Web page: https://patentgrep.com/patent/US12191250B2

## CPC

- H10B 61/22: {of the field-effect transistor [FET] type}
- H10W 20/42: Vias, e.g. via plugs
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10P 52/403: {of conductive or resistive materials}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/076: {in via holes or trenches}
- H10W 20/43: Layouts of interconnections
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates integrated chip structure. The integrated chip structure includes a lower insulating structure disposed over a lower dielectric structure surrounding one or more lower interconnects. A bottom electrode via surrounded by one or more interior sidewalls of the lower insulating structure. The bottom electrode via includes a barrier surrounding a conductive core. A bottom electrode is arranged on the bottom electrode via, a data storage structure is over the bottom electrode, and a top electrode is over the data storage structure. The barrier includes a sidewall disposed along the one or more interior sidewalls of the lower insulating structure and a horizontally covering segment protruding outward from the sidewall to above a top surface of the lower insulating structure.

## Claims

### Claim 1

A method of forming an integrated chip structure, comprising:
forming a lower insulating structure over a lower dielectric structure surrounding one or more lower interconnects;
patterning the lower insulating structure to form a bottom electrode via opening exposing the one or more lower interconnects;
forming a barrier layer within the bottom electrode via opening and over the lower insulating structure;
forming a conductive core material over the barrier layer;
performing a mechanical polishing process to remove a first part of the conductive core material;
performing a buffing process to remove a second part of the conductive core material and to form a conductive core;
forming a bottom electrode layer onto the conductive core and the barrier layer;
forming a data storage layer onto the bottom electrode layer; and
forming a top electrode layer onto the data storage layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
utilizing a focused ion beam etching (FIBE) process to pattern the top electrode layer, the data storage layer, the bottom electrode layer, the barrier layer, and the lower insulating structure.

### Claim 3 (depends on 2)

The method of claim 2, wherein the FIBE process causes the lower insulating structure to have one or more curved outer sidewalls that face away from the conductive core and that are coupled to a top surface of the lower insulating structure.

### Claim 4 (depends on 1)

The method of claim 1, wherein the mechanical polishing process forms a dished region of the conductive core material that is recessed below a top of the barrier layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the mechanical polishing process forms one or more fang defects having a first depth arranged along outer edges of the conductive core material.

### Claim 6 (depends on 5)

The method of claim 5, wherein the buffing process reduces the first depth of the one or more fang defects to a second depth that is less than the first depth.

### Claim 7 (depends on 1)

The method of claim 1, wherein the buffing process is performed using a slurry that is devoid of an oxidizer.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming an intermediate glue layer onto the barrier layer; and
forming the conductive core material onto the intermediate glue layer.

### Claim 9 (depends on 1)

The method of claim 1, wherein the buffing process causes the barrier layer to have a first thickness within an embedded memory region comprising the bottom electrode via opening and a second thickness in a peripheral region outside of the embedded memory region, the second thickness being greater than the first thickness.

### Claim 10

A method, comprising:
forming a lower insulating structure over a lower dielectric structure surrounding one or more lower interconnects;
forming a bottom electrode via opening to extend through the lower insulating structure and expose the one or more lower interconnects;
forming a barrier layer within the bottom electrode via opening;
forming a glue layer over the barrier layer;
forming a conductive core over the glue layer;
forming a memory device stack over the conductive core, the glue layer, and the barrier layer; and
patterning the memory device stack and the barrier layer to form a memory device over a barrier and the glue layer, wherein the barrier comprises a sidewall disposed along an interior sidewall of the lower insulating structure and a horizontally extending segment protruding outward from the sidewall to above a top surface of the lower insulating structure, after the patterning is complete.

### Claim 11 (depends on 10)

The method of claim 10, wherein the memory device comprises a data storage structure arranged between a top electrode and a bottom electrode, the bottom electrode contacting top surfaces of both the glue layer and the barrier.

### Claim 12 (depends on 11)

The method of claim 11, wherein the barrier has an outermost sidewall that is directly below a lower surface of the bottom electrode and directly above the top surface of the lower insulating structure.

### Claim 13 (depends on 12)

The method of claim 12, wherein the outermost sidewall of the barrier is laterally separated from an outermost sidewall of the bottom electrode by a non-zero distance.

### Claim 14 (depends on 10)

The method of claim 10, wherein the top surface of the lower insulating structure laterally extends past an outermost sidewall of the barrier.

### Claim 15

A method, comprising:
forming one or more interconnects within an inter-level dielectric (ILD) structure;
patterning an upper surface of the ILD structure to form a bottom electrode via opening exposing the one or more interconnects;
forming a barrier layer within the bottom electrode via opening and over the ILD structure;
forming a conductive core material over the barrier layer;
performing a mechanical polishing process to remove a first part of the conductive core material and expose an upper surface of the barrier layer, wherein the upper surface of the barrier layer is directly over the upper surface of the ILD structure after the mechanical polishing process;
performing a buffing process to remove a second part of the conductive core material and to form a conductive core; and
forming a memory device over the conductive core.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
forming an intermediate glue layer over the barrier layer, wherein the conductive core material is formed onto the intermediate glue layer; and
wherein the mechanical polishing process exposes an upper surface of the intermediate glue layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein the mechanical polishing process also removes parts of the barrier layer and the intermediate glue layer.

### Claim 18 (depends on 15)

The method of claim 15, wherein the barrier layer comprises a sidewall and a horizontally extending segment protruding outward from the sidewall after the buffing process is completed.

### Claim 19 (depends on 15)

The method of claim 15, wherein the mechanical polishing process utilizes a first slurry that comprises an oxidizer and the buffing process utilizes a second slurry that is devoid of an oxidizer.

### Claim 20 (depends on 15)

The method of claim 15,
wherein the conductive core material comprises recessed areas along outer edges of the conductive core material after the mechanical polishing process; and
wherein the buffing process reduces a depth of the recessed areas.