# US 12,191,248 B2 · Semiconductor arrangement and method of making

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- Number: US 12,191,248 B2
- Document ID: US12191248B2
- Status: Granted
- Kind: B2
- Application number: 17/335,242
- Filed: 2021-06-01
- Published: 2022-09-08
- Granted: 2025-01-07
- Earliest claimed: 2021-03-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Limited
- Inventors: Wan-Yu Lo; Chung-Hsing Wang; Chin-Shen Lin; Kuo-Nan Yang; Hsiang-Ku Shen; Dian-Hau Chen
- Web page: https://patentgrep.com/patent/US12191248B2

## CPC

- H10W 20/496: {Capacitor integral with wiring layers}
- H10D 1/68: Capacitors having no potential barriers
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a semiconductor arrangement includes forming a first capacitor in a first voltage domain and forming a second capacitor in the first voltage domain. The first capacitor is connected in parallel with the second capacitor. A third capacitor and a fourth capacitor are formed in a second voltage domain. The third capacitor is connected in series with the fourth capacitor. The first capacitor and the second capacitor are connected in parallel with a supply terminal of the first voltage domain and a reference terminal of the first voltage domain. The fourth capacitor is connected to a supply terminal of the second voltage domain. The third capacitor is connected to a reference terminal of the second voltage domain.

## Claims

### Claim 1

A semiconductor arrangement, comprising:
a first conductive plate;
a first portion of a dielectric material over the first conductive plate;
a second conductive plate over the first portion of the dielectric material;
a second portion of the dielectric material over the second conductive plate;
a third conductive plate over the second portion of the dielectric material;
a third portion of the dielectric material over the third conductive plate;
a fourth conductive plate over the third portion of the dielectric material;
a fourth portion of the dielectric material over the fourth conductive plate;
a fifth conductive plate over the fourth portion of the dielectric material;
a first conductive via directly physically contacting the first conductive plate and the fifth conductive plate;
a second conductive via directly physically contacting the third conductive plate; and
a third conductive via directly physically contacting the second conductive plate and the fourth conductive plate.

### Claim 2 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a supply terminal; and
a reference terminal, wherein:
the first conductive via is connected to the supply terminal, and
the second conductive via is connected to the reference terminal.

### Claim 3 (depends on 2)

The semiconductor arrangement of claim 2, comprising:
a voltage source, wherein:
the supply terminal is connected to the voltage source to receive a supply voltage from the voltage source, and
the supply voltage is greater than a breakdown voltage of the dielectric material.

### Claim 4 (depends on 1)

The semiconductor arrangement of claim 1, comprising:
a supply terminal; and
a reference terminal, wherein:
the first conductive via is connected to the supply terminal,
the second conductive via is connected to the supply terminal, and
the third conductive via is connected to the reference terminal.

### Claim 5 (depends on 4)

The semiconductor arrangement of claim 4, wherein:
the supply terminal is connected to a voltage source to receive a supply voltage from the voltage source, and
the supply voltage is less than a breakdown voltage of the dielectric material.

### Claim 6 (depends on 1)

The semiconductor arrangement of claim 1, wherein:
the dielectric material comprises a high-k dielectric material.

### Claim 7

A semiconductor arrangement, comprising:
a first voltage domain connected to at least one of a core region or a logic region configured to operate at a first supply voltage, the first voltage domain comprising:
a first supply terminal for receiving the first supply voltage from a first voltage source;
a first reference terminal; and
a first capacitor network connected across the first supply terminal and the first reference terminal and comprising a stack of alternating layers of a conductive material having a first thickness and a dielectric material having a second thickness, wherein the first supply voltage is less than a breakdown voltage of the dielectric material having the second thickness; and
a second voltage domain connected to an input/output region configured to operate at a second supply voltage different than the first supply voltage, the second voltage domain comprising:
a second supply terminal for receiving the second supply voltage from a second voltage source;
a second reference terminal; and
a second capacitor network connected across the second supply terminal and the second reference terminal and comprising the stack of alternating layers of the conductive material having the first thickness and the dielectric material having the second thickness, wherein the second supply voltage is greater than the breakdown voltage of the dielectric material having the second thickness.

### Claim 8 (depends on 7)

The semiconductor arrangement of claim 7, wherein:
the first capacitor network defines a first capacitor and a second capacitor connected in parallel across the first supply terminal and the first reference terminal.

### Claim 9 (depends on 7)

The semiconductor arrangement of claim 7, wherein:
the stack of alternating layers comprises a first conductive layer, a second conductive layer over the first conductive layer and defining a first capacitor, a third conductive layer over the second conductive layer and defining a second capacitor, a fourth conductive layer over the third conductive layer and defining a third capacitor, and a fifth conductive layer over the fourth conductive layer and defining a fourth capacitor, and
the first capacitor, the second capacitor, the third capacitor, and the fourth capacitor are connected in parallel across the first supply terminal and the first reference terminal.

### Claim 10 (depends on 9)

The semiconductor arrangement of claim 9, wherein:
the first capacitor network comprises:
a first conductive via coupled to the first conductive layer, the third conductive layer, the fifth conductive layer, and the first supply terminal; and
a second conductive via coupled to the second conductive layer, the fourth conductive layer, and the first reference terminal.

### Claim 11 (depends on 9)

The semiconductor arrangement of claim 9, wherein:
the first capacitor network comprises:
a first conductive via coupled to the first conductive layer, the fifth conductive layer, and the first supply terminal;
a second conductive via coupled to the second conductive layer, the fourth conductive layer, and the first reference terminal; and
a third conductive via coupled to the third conductive layer and the first supply terminal.

### Claim 12 (depends on 7)

The semiconductor arrangement of claim 7, wherein:
the stack of alternating layers comprises a first conductive layer, a second conductive layer over the first conductive layer and defining a first capacitor, a third conductive layer over the second conductive layer and defining a second capacitor, a fourth conductive layer over the third conductive layer and defining a third capacitor, and a fifth conductive layer over the fourth conductive layer and defining a fourth capacitor,
the first capacitor and the second capacitor are connected in series, and
the third capacitor and the fourth capacitor are connected in series.

### Claim 13 (depends on 12)

The semiconductor arrangement of claim 12, wherein:
a first intermediate node defined between the first capacitor and the second capacitor is connected to a second intermediate node defined between the third capacitor and the fourth capacitor.

### Claim 14 (depends on 12)

The semiconductor arrangement of claim 12, wherein:
the first capacitor network comprises:
a first conductive via coupled to the first conductive layer, the fifth conductive layer, and the second supply terminal;
a second conductive via coupled to the second conductive layer and the fourth conductive layer; and
a third conductive via coupled to the third conductive layer and the second reference terminal.

### Claim 15

A semiconductor arrangement, comprising:
a first voltage domain connected to at least one of a core region or a logic region configured to operate at a first supply voltage, the first voltage domain comprising:
a first capacitor;
a second capacitor connected in parallel with the first capacitor;
a first supply terminal for receiving the first supply voltage from a first voltage source;
a first reference terminal, wherein the first capacitor and the second capacitor are connected in parallel with the first supply terminal and the first reference terminal;
a second voltage domain connected to an input/output region configured to operate at a second supply voltage different than the first supply voltage, the second voltage domain comprising:
a third capacitor;
a fourth capacitor connected in series with the third capacitor;
a second supply terminal for receiving the second supply voltage; and
a second reference terminal connected to the third capacitor.

### Claim 16 (depends on 15)

The semiconductor arrangement of claim 15, wherein:
at least one of the first capacitor, the second capacitor, the third capacitor, or the fourth capacitor comprise a dielectric material.

### Claim 17 (depends on 16)

The semiconductor arrangement of claim 16, wherein the dielectric material comprises a high-k dielectric material.

### Claim 18 (depends on 16)

The semiconductor arrangement of claim 16, wherein:
the first supply voltage is less than a breakdown voltage of the dielectric material, and
the second supply voltage is greater than the breakdown voltage of the dielectric material.

### Claim 19 (depends on 18)

The semiconductor arrangement of claim 18, wherein:
the first capacitor comprises:
a first conductive plate;
a first portion of the dielectric material over the first conductive plate; and
a second conductive plate over the first portion of the dielectric material and the first conductive plate,
the second capacitor comprises:
a second portion of the dielectric material over the second conductive plate; and
a third conductive plate over the second portion of the dielectric material and the second conductive plate, and
the semiconductor arrangement comprises:
a first conductive via connecting the first conductive plate to the third conductive plate and connected to the first supply terminal; and
a second conductive via connected to the second conductive plate and the first reference terminal.

### Claim 20 (depends on 18)

The semiconductor arrangement of claim 18, wherein:
the third capacitor comprises:
a first conductive plate;
a first portion of the dielectric material over the first conductive plate; and
a second conductive plate over the first portion of the dielectric material and the first conductive plate,
the fourth capacitor comprises:
a second portion of the dielectric material over the second conductive plate; and
a third conductive plate over the second portion of the dielectric material and the second conductive plate, and
the semiconductor arrangement comprises:
a first conductive via connected to the third conductive plate and connected to the second supply terminal; and
a second conductive via connected to the first conductive plate and the second reference terminal.