# US 12,191,245 B2 · Semiconductor device having a curved part in the printed circuit board

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- Number: US 12,191,245 B2
- Document ID: US12191245B2
- Status: Granted
- Kind: B2
- Application number: 17/731,861
- Filed: 2022-04-28
- Published: 2022-12-22
- Granted: 2025-01-07
- Earliest claimed: 2021-06-16
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Motohito Hori; Yoshinari Ikeda; Akio Toba; Michio Tamate; Ikuya Sato
- Web page: https://patentgrep.com/patent/US12191245B2

## CPC

- H10W 70/611: {for connecting multiple chips together}
- H10W 70/688: {Flexible insulating substrates}
- C04B 37/021: {in a direct manner, e.g. direct copper bonding [DCB]}
- C04B 37/026: {consisting of metals or metal salts}
- H10W 40/255: {having a laminate or multilayered structure, e.g. direct bond copper [DBC] ceramic substrates}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/00: Interconnections or connectors in packages
- H10W 72/0711: {Apparatus therefor}
- H10W 90/00: Package configurations
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- C04B 2237/12: Metallic interlayers
- C04B 2237/343: Alumina or aluminates
- C04B 2237/361: Boron nitride
- C04B 2237/366: Aluminium nitride
- C04B 2237/368: Silicon nitride
- C04B 2237/407: Copper
- H05K 1/0306: {Inorganic insulating substrates, e.g. ceramic, glass}
- H05K 1/147: {at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit (H05K1/148 takes precedence)}
- H05K 1/189: characterised by the use of flexible or folded printed circuits
- H10W 40/611: {Bolts or screws}
- H10W 72/01225: {in solid form, e.g. by using a powder or by stud bumping}
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07331: {Connecting techniques}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/551: {Materials of bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- C04B: LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE {(roofing granules E04D7/005)}; CERAMICS (devitrified glass-ceramics C03C10/00); REFRACTORIES; TREATMENT OF NATURAL STONE
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A semiconductor device includes: an insulated circuit substrate including first and second conductive layers on a top surface side; a first semiconductor chip mounted on the first conductive layer; a second semiconductor chip mounted on the second conductive layer; a printed circuit board including a first lower-side wiring layer arranged to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate; a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer; a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer; and a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part.

## Claims

### Claim 1

A semiconductor device comprising:
an insulated circuit substrate including first and second conductive layers on a top surface side;
a first semiconductor chip mounted on the first conductive layer;
a second semiconductor chip mounted on the second conductive layer;
a printed circuit board including an insulating layer, a first lower-side wiring layer arranged on one main surface of the insulating layer so as to be opposed to the first semiconductor chip, and a second lower-side wiring layer arranged on the one main surface of the insulating layer so as to be opposed to the second semiconductor chip, the printed circuit board being provided with a curved part curved toward the insulated circuit substrate;
a first connection member arranged to connect the first semiconductor chip with the first lower-side wiring layer;
a second connection member arranged to connect the second semiconductor chip with the second lower-side wiring layer;
a third connection member arranged to connect the first conductive layer with the second lower-side wiring layer at the curved part; and
a sealing member provided to seal the first and second semiconductor chips, the printed circuit board, and the first to third connection members.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first to third connection members have heights common to each other.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the curved part has a step having a thickness common to a total thickness of the first semiconductor chip and a bonding material bonding the first semiconductor chip and the first conductive layer to each other.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the curved part is located in a middle part of the printed circuit board in a longitudinal direction.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the insulating layer is formed from resin.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the insulated circuit substrate includes a resin substrate having a top surface on which the first and second conductive layers are deposited.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, further comprising a first external connection terminal integrated with the second conductive layer and externally extending from the sealing member.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first lower-side wiring layer is electrically connected to a main electrode of the first semiconductor chip, and
the second lower-side wiring layer is electrically connected to a main electrode of the second semiconductor chip.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the printed circuit board includes:
a first upper-side wiring layer deposited on a top surface of the insulating layer at a position overlapping with the first lower-side wiring layer via the insulating layer so as to be electrically connected to the first lower-side wiring layer; and
a second upper-side wiring layer deposited on the top surface of the insulating layer at a position overlapping with the second lower-side wiring layer via the insulating layer so as to be electrically connected to the second lower-side wiring layer.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, further comprising a second external connection terminal connected to the first upper-side wiring layer.

### Claim 11 (depends on 10)

The semiconductor device of claim 10, further comprising a third external connection terminal connected to the second upper-side wiring layer.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein the printed circuit board includes:
a third lower-side wiring layer deposited on a bottom surface of the insulating layer and electrically connected to a first main electrode of the first semiconductor chip; and
a third upper-side wiring layer deposited on the top surface of the insulating layer at a position overlapping with the third lower-side wiring layer via the insulating layer so as to be electrically connected to a control electrode of the first semiconductor chip, and
the third lower-side wiring layer and the third upper-side wiring layer have current paths opposite to each other.

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein the printed circuit board is provided with a slit at a position corresponding to the curved part.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the printed circuit board is provided with a notch at a position corresponding to the curved part.