# US 12,191,239 B2 · Stacked via structure disposed on a conductive pillar of a semiconductor die

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,191,239 B2
- Document ID: US12191239B2
- Status: Granted
- Kind: B2
- Application number: 18/357,987
- Filed: 2023-07-24
- Published: 2023-11-16
- Granted: 2025-01-07
- Earliest claimed: 2021-04-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Che-Yu Yeh; Tsung-Shu Lin; Wei-Cheng Wu; Tsung-Yu Chen; Li-Han Hsu; Chien-Fu Tseng
- Web page: https://patentgrep.com/patent/US12191239B2

## CPC

- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/685: comprising multiple insulating layers
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 90/722: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A stacked via structure disposed on a conductive pillar of a semiconductor die is provided. The stacked via structure includes a first dielectric layer, a first conductive via, a first redistribution wiring, a second dielectric layer, a second conductive via, and a second redistribution wiring. The first dielectric layer covers the semiconductor die. The first conductive via is embedded in the first dielectric layer and electrically connected to the conductive pillar. The first redistribution wiring covers the first conductive via and the first dielectric layer. The second dielectric layer covers the first dielectric layer and the first redistribution wiring. The second conductive via is embedded in the second dielectric layer and landed on the first redistribution wiring. The second redistribution wiring covers the second conductive via and the second dielectric layer. A lateral dimension of the first conductive via is greater than a lateral dimension of the second conductive via.

## Claims

### Claim 1

A stacked via structure, disposed on a conductive pillar of a semiconductor die, the stacked via structure comprising:
a first dielectric layer disposed on the semiconductor die;
a first conductive via embedded in the first dielectric layer, wherein the first conductive via is in physical contact with the conductive pillar of the semiconductor die;
a first redistribution wiring disposed on the first conductive via and the first dielectric layer;
a second dielectric layer disposed over the first dielectric layer and the first redistribution wiring;
a second conductive via embedded in the second dielectric layer, wherein the second conductive via is electrically connected to the conductive pillar of the semiconductor die through the first redistribution wiring; and
a second redistribution wiring disposed on the second conductive via and the second dielectric layer, wherein a first lateral dimension of the first conductive via is greater than a second lateral dimension of the second conductive via.

### Claim 2 (depends on 1)

The stacked via structure as claimed in claim 1 further comprising:
a third dielectric layer disposed on the second dielectric layer and the second redistribution wiring;
a third conductive via embedded in the third dielectric layer and landed on the second redistribution wiring; and
a third redistribution wiring disposed on the third conductive via and the third dielectric layer.

### Claim 3 (depends on 2)

The stacked via structure as claimed in claim 2, wherein the second lateral dimension of the second conductive via is greater than a third lateral dimension of the third conductive via.

### Claim 4 (depends on 2)

The stacked via structure as claimed in claim 2, wherein the second lateral dimension of the second conductive via is substantially equal to a third lateral dimension of the third conductive via.

### Claim 5 (depends on 2)

The stacked via structure as claimed in claim 2 further comprising:
a fourth dielectric layer disposed on the third dielectric layer and the third redistribution wiring;
a fourth conductive via embedded in the fourth dielectric layer and landed on the third redistribution wiring; and
a fourth redistribution wiring disposed on the fourth conductive via and the fourth dielectric layer.

### Claim 6 (depends on 5)

The stacked via structure as claimed in claim 5, wherein the third lateral dimension of the third conductive via is greater than a fourth lateral dimension of the fourth conductive via.

### Claim 7 (depends on 5)

The stacked via structure as claimed in claim 5, wherein the third lateral dimension of the third conductive via is substantially equal to a fourth lateral dimension of the fourth conductive via.

### Claim 8 (depends on 1)

The stacked via structure as claimed in claim 1, wherein the first conductive via comprises first tapered sidewalls, and the second conductive via comprises second tapered sidewalls.

### Claim 9 (depends on 1)

The stacked via structure as claimed in claim 1, wherein the first conductive via comprises first vertical sidewalls, and the second conductive via comprises second vertical sidewalls.

### Claim 10 (depends on 1)

The stacked via structure as claimed in claim 1, wherein a first centerline of the first conductive via is substantially aligned with a second centerline of the second conductive via.

### Claim 11 (depends on 1)

The stacked via structure as claimed in claim 1, wherein a first centerline of the first conductive via is offset from a second centerline of the second conductive via.

### Claim 12

A stacked via structure, disposed on a surface of a semiconductor die, the stacked via structure comprising:
a first dielectric layer disposed on the semiconductor die;
a first conductive via embedded in the first dielectric layer, wherein the first conductive via is in physical contact with the surface of the semiconductor die;
a first redistribution wiring disposed on the first conductive via and the first dielectric layer;
a second dielectric layer disposed on the first dielectric layer and the first redistribution wiring;
a second conductive via embedded in the second dielectric layer, wherein the second conductive via is electrically connected to the semiconductor die through the first redistribution wiring; and
a second redistribution wiring disposed on the second conductive via and the second dielectric layer, wherein a first contact area of the first conductive via and the semiconductor die is greater than a second contact area of the second conductive via and the first redistribution wiring.

### Claim 13 (depends on 12)

The stacked via structure as claimed in claim 12 further comprising:
a third dielectric layer disposed on the second dielectric layer and the second redistribution wiring;
a third conductive via embedded in the third dielectric layer and landed on the second redistribution wiring; and
a third redistribution wiring disposed on the third conductive via and the third dielectric layer, wherein the second contact area is greater than or equal to a third contact area of the third conductive via and the second redistribution wiring.

### Claim 14 (depends on 13)

The stacked via structure as claimed in claim 13 further comprising:
a fourth dielectric layer disposed on the third dielectric layer and the third redistribution wiring;
a fourth conductive via embedded in the fourth dielectric layer and landed on the third redistribution wiring; and
a fourth redistribution wiring disposed on the fourth conductive via and the fourth dielectric layer, wherein the third contact area is greater than or equal to a fourth contact area of the fourth conductive via and the third redistribution wiring.

### Claim 15 (depends on 12)

The stacked via structure as claimed in claim 12, wherein the first conductive via comprises tapered sidewalls or vertical sidewalls, and the second conductive via comprises tapered sidewalls or vertical sidewalls.

### Claim 16 (depends on 12)

The stacked via structure as claimed in claim 12, wherein a first centerline of the first conductive via is substantially aligned with a second centerline of the second conductive via.

### Claim 17 (depends on 12)

The stacked via structure as claimed in claim 12, wherein a first centerline of the first conductive via is offset from a second centerline of the second conductive via.

### Claim 18

A structure, comprising:
a semiconductor die comprising conductive terminals;
conductive through vias;
an insulating encapsulation laterally encapsulating the semiconductor die and the conductive through vias;
a redistribution circuit structure, comprising:
stacked dielectric layers covering the semiconductor die and the insulating encapsulation;
a first conductive via embedded in a bottommost dielectric layer among the stacked dielectric layers, wherein the first conductive via is in physical contact with at least one of the conductive terminals or the conductive through vias;
a first redistribution wiring disposed on the first conductive via and the first dielectric layer;
a second conductive via embedded in an upper dielectric layer among the stacked dielectric layers, wherein the second conductive via is electrically connected to the at least one of the conductive terminals or the conductive through vias through the first redistribution wiring; and
a second redistribution wiring disposed on the second conductive via, wherein a first lateral dimension of the first conductive via is greater than a second lateral dimension of the second conductive via.

### Claim 19 (depends on 18)

The structure as claimed in claim 18, wherein a first centerline of the first conductive via is offset from a second centerline of the second conductive via.

### Claim 20 (depends on 18)

The structure as claimed in claim 18, wherein a first centerline of the first conductive via is substantially aligned with a second centerline of the second conductive via.