# US 12,191,238 B2 · Semiconductor package

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- Number: US 12,191,238 B2
- Document ID: US12191238B2
- Status: Granted
- Kind: B2
- Application number: 18/167,369
- Filed: 2023-02-10
- Published: 2023-06-15
- Granted: 2025-01-07
- Earliest claimed: 2020-09-07
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Aenee Jang
- Web page: https://patentgrep.com/patent/US12191238B2

## CPC

- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/095: {of vias therein}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 70/685: comprising multiple insulating layers
- H10W 70/687: {characterized by the outer layers being for protection, e.g. solder masks, or for protection against chemical or mechanical damage}
- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 72/90: Bond pads, in general
- H10W 74/137: {the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence)}
- H10W 90/00: Package configurations
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/69: Insulating materials thereof
- H10W 72/072: {of bump connectors}
- H10W 72/07254: {changes in dispositions}
- H10W 72/073: {of die-attach connectors}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/253: {not comprising solid metals or solid metalloids, e.g. polymers or ceramics}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/951: {Materials of bond pads}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package includes a base substrate; an interposer substrate including a semiconductor substrate having a first surface facing the base substrate and a second surface, opposing the first surface, and a passivation layer on at least a portion of the first surface; a plurality of connection bumps between the base substrate and the interposer substrate; an underfill resin in a space between the base substrate and the interposer substrate; and a first semiconductor chip and a second semiconductor chip on the interposer substrate. The interposer substrate has a first region, in which the plurality of connection bumps are included, and a second region and a third region adjacent a periphery of the first region, and the passivation layer is in the second region and includes a first embossed pattern in the second region.

## Claims

### Claim 1

A semiconductor package comprising:
an interposer substrate having a first region comprising a plurality of through-vias, a second region adjacent to a periphery of the first region and spaced apart from an edge of the interposer substrate, and a third region disposed between the second region and the edge of the interposer substrate;
a passivation layer on a first surface of the interposer substrate in the first region and the second region;
a plurality of dummy patterns on the first surface of the interposer substrate in at least one of the first region and the second region, and embedded in the passivation layer;
first and second semiconductor chips on a second surface of the interposer substrate opposite to the first surface; and
an underfill resin in contact with at least a portion of the first surface of the interposer substrate in the third region, and at least a portion of the edge of the interposer substrate between the first surface and the second surface.

### Claim 2 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the second region has a width greater than a width of the third region.

### Claim 3 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the third region is within a predetermined distance of the edge of the interposer substrate.

### Claim 4 (depends on 3)

The semiconductor package as claimed in claim 3, wherein the predetermined distance is about 10 μm or more.

### Claim 5 (depends on 1)

The semiconductor package as claimed in claim 1, wherein a height of the passivation layer is about 1 μm or more.

### Claim 6 (depends on 1)

The semiconductor package as claimed in claim 1, further comprising:
a base substrate below the interposer substrate; and
a plurality of connection bumps between the base substrate and the interposer substrate and a plurality of bump pads on the first surface of the interposer substrate in the first region to the base substrate.

### Claim 7 (depends on 6)

The semiconductor package as claimed in claim 6, wherein the plurality of dummy patterns includes a metal the same as that of the plurality of connection bumps.

### Claim 8 (depends on 1)

The semiconductor package as claimed in claim 1, wherein the passivation layer includes a plurality of embossed patterns vertically aligned with respect to the plurality of dummy patterns.

### Claim 9

A semiconductor package comprising:
a base substrate comprising a first interconnection structure;
an interposer substrate comprising a semiconductor substrate having a first surface facing the base substrate and a second surface opposing the first surface, an interconnection region on the second surface and comprising a second interconnection structure, a plurality of through-vias extending through the semiconductor substrate and electrically connecting the second interconnection structure to the first interconnection structure, and a passivation layer on at least a portion of the first surface;
a plurality of connection bumps between the base substrate and the interposer substrate and electrically connecting the plurality of through-vias to the first interconnection structure;
a plurality of dummy patterns on the first surface of the interposer substrate, and embedded in the passivation layer;
an underfill resin in a space between the base substrate and the interposer substrate; and
first and second semiconductor chips on the interconnection region of the interposer substrate and electrically connected to each other by the second interconnection structure,
wherein the interposer substrate comprises a first region comprising the plurality of through-vias, a second region adjacent a periphery of the first region, and a third region adjacent a periphery of the second region,
the first region and the second region include the passivation layer thereon, and
the third region is free of the passivation layer.

### Claim 10 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the plurality of dummy patterns are electrically insulated from the plurality of connection bumps.

### Claim 11 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the plurality of dummy patterns are disposed in at least one of the first region and the second region.

### Claim 12 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the underfill resin is in contact with a portion of the first surface of the interposer substrate in the third region, and a portion of an edge of the interposer substrate between the first surface and the second surface.

### Claim 13 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the third region is within about 10 μm to about 50 μm from an edge of the interposer substrate.

### Claim 14 (depends on 9)

The semiconductor package as claimed in claim 9, wherein a height of the passivation layer is about 1 μm to about 5 μm.

### Claim 15 (depends on 9)

The semiconductor package as claimed in claim 9, wherein the plurality of dummy patterns includes a metal.

### Claim 16

A semiconductor package comprising:
an interposer substrate having a first surface, a second surface opposing the first surface, and a side surface between the first surface and the second surface;
a passivation layer on a portion of the first surface of the interposer substrate;
first and second semiconductor chips on a second surface of the interposer substrate opposite the first surface, and electrically connected to each other through the interposer substrate; and
an underfill resin in contact with at least a portion of the first surface of the interposer substrate that is exposed by the passivation layer, and at least a portion of the side surface of the interposer substrate.

### Claim 17 (depends on 16)

The semiconductor package as claimed in claim 16, wherein the passivation layer is spaced apart from an edge of the interposer substrate by about 10 μm or more.

### Claim 18 (depends on 16)

The semiconductor package as claimed in claim 16, wherein a height of the passivation layer is about 1 μm or more.

### Claim 19 (depends on 16)

The semiconductor package as claimed in claim 16, wherein the interposer substrate further has a first region comprising a plurality of through-vias, a second region adjacent a periphery of the first region and spaced apart from the side surface of the interposer substrate, and a third region between the second region and the side surface of the interposer substrate.

### Claim 20 (depends on 19)

The semiconductor package as claimed in claim 19, wherein the passivation layer is in contact with the first surface of the interposer substrate in the first region and the second region.