# US 12,191,235 B2 · Integrated cooling assemblies including signal redistribution and methods of manufacturing the same

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- Number: US 12,191,235 B2
- Document ID: US12191235B2
- Status: Granted
- Kind: B2
- Application number: 18/512,567
- Filed: 2023-11-17
- Published: 2024-11-21
- Granted: 2025-01-07
- Earliest claimed: 2023-05-17
- Assignees: Adeia Semiconductor Bonding Technologies Inc.
- Applicants: Adeia Semiconductor Bonding Technologies Inc.
- Inventors: Belgacem Haba; Rajesh Katkar
- Web page: https://patentgrep.com/patent/US12191235B2

## CPC

- H10W 40/47: by flowing liquids, e.g. forced water cooling
- H10B 80/00: Assemblies of multiple devices comprising at least one memory device covered by this subclass
- H10W 40/73: for cooling by change of state
- H10W 70/635: {Through-vias}
- H10W 70/685: comprising multiple insulating layers
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/791: {of direct-bonded pads}
- H10W 90/794: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present disclosure provides for integrated cooling systems including an integrated cooling assembly. The integrated cooling assembly includes a semiconductor device having an active side and a backside opposite the active side. The integrated cooling assembly includes a plurality of stacked and bonded layers that collectively form a cold plate, the cold plate comprising (i) a first side and a second side opposite the first side, the first side having a base surface, a support feature that extends downwardly from the base surface, and sidewalls that extend downwardly from the base surface and surround base surface and the support feature, and (ii) a first interconnect vertically disposed through the support feature, where the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the cold plate and the semiconductor device.

## Claims

### Claim 1

A device package comprising:
a semiconductor device having an active side and a backside opposite the active side; and
a plurality of bonded layers, comprising:
a first layer and a second layer, the first layer having a recessed surface, a support feature that extends downwardly from the recessed surface to the second layer, and sidewalls that extend downwardly from the recessed surface to the second layer and surround the recessed surface and the support feature; and
a first interconnect vertically disposed through the support feature, wherein the first interconnect is electrically coupled to the semiconductor device through direct hybrid bonds formed between the second layer and the semiconductor device.

### Claim 2 (depends on 1)

The device package of claim 1, wherein the plurality of bonded layers collectively forms a cold plate, and wherein the first layer and the second layer of the cold plate define a coolant channel therebetween.

### Claim 3 (depends on 2)

The device package of claim 2, wherein the support feature is disposed in the coolant channel, and sidewalls of the support feature define a plurality of flow paths.

### Claim 4 (depends on 2)

The device package of claim 2, wherein the cold plate is an interposer, and the device package further comprises a plurality of semiconductor devices communicatively coupled to one another through the interposer.

### Claim 5 (depends on 4)

The device package of claim 4, wherein two or more of the plurality of semiconductor devices are coupled to opposite sides of the cold plate by direct hybrid bonds.

### Claim 6 (depends on 4)

The device package of claim 4, wherein at least two of the plurality of semiconductor devices are bonded to the interposer in a side-by-side arrangement.

### Claim 7 (depends on 1)

The device package of claim 1, wherein the plurality of bonded layers comprises a power plane and/or a ground plane.

### Claim 8 (depends on 7)

The device package of claim 7, wherein the first interconnect connects the semiconductor device to at least one of the power plane or the ground plane.

### Claim 9 (depends on 1)

The device package of claim 1, wherein the support feature decreases in width from the recessed surface to the second layer.

### Claim 10 (depends on 1)

The device package of claim 1, wherein the plurality of bonded layers comprises a plurality of interconnects forming a signal redistribution network that is communicatively coupled to input/output (I/O) features of the semiconductor device through the direct hybrid bonds.

### Claim 11 (depends on 1)

The device package of claim 1, further comprising:
a conductive layer disposed on the recessed surface and the support feature; and
a dielectric layer disposed over the conductive layer.

### Claim 12 (depends on 1)

The device package of claim 1, wherein:
the plurality of bonded layers comprises a stack of layers, each layer of the stack of layers being directly hybrid bonded to one or more respectively adjacent layers of the stack of layers;
each of the stack of layers comprises a segment of the first interconnect; and
each segment of the first interconnect is connected to another vertically adjacent segment of the first interconnect through the direct hybrid bonds formed between the adjacent layers of the stack of layers.

### Claim 13

A microelectronic package comprising:
a plurality of bonded layers comprising:
a first layer and a second layer, the first layer having a recessed surface, sidewalls that surround the recessed surface and extend downwardly therefrom to define a cavity between the first layer and the second layer, and a support feature disposed in the cavity; and
a first interconnect vertically disposed through the support feature, wherein:
the first interconnect is electrically coupled to a device through direct hybrid bonds formed between the second layer and a backside of the device; and
the first layer and the second layer of the plurality of bonded layers define a coolant channel therebetween.

### Claim 14 (depends on 13)

The microelectronic package of claim 13, wherein the plurality of bonded layers collectively forms a cold plate.

### Claim 15 (depends on 13)

The microelectronic package of claim 13, wherein:
a third layer of the plurality of bonded layers comprises a second interconnect vertically disposed therethrough; and
the first and second interconnects are electrically coupled through direct hybrid bonds formed between the first layer and the third layer.

### Claim 16 (depends on 13)

The microelectronic package of claim 13, wherein the second layer is directly bonded to the device through the direct hybrid bonds.

### Claim 17 (depends on 13)

The microelectronic package of claim 13, wherein the support feature decreases in width from the recessed surface to a bonding interface of the first layer and the second layer.

### Claim 18 (depends on 13)

The microelectronic package of claim 13, wherein:
the plurality of bonded layers comprises a stack of layers, each layer of the stack of layers being directly hybrid bonded to one or more respectively adjacent layers of the stack of layers;
each of the stack of layers comprises a segment of the first interconnect; and
each segment of the first interconnect is connected to another vertically adjacent segment of the first interconnect through the direct hybrid bonds formed between the adjacent layers of the stack of layers.

### Claim 19 (depends on 13)

The microelectronic package of claim 13, wherein the plurality of bonded layers comprises an interposer having interconnections between the device and one or more other devices.

### Claim 20 (depends on 13)

The microelectronic package of claim 13, wherein sidewalls of the support feature disposed in the cavity define a plurality of flow paths.