# US 12,191,226 B2 · Method of manufacturing heat dissipation substrate with high thermal conductivity for semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,226 B2 - Document ID: US12191226B2 - Status: Granted - Kind: B2 - Application number: 18/155,322 - Filed: 2023-01-17 - Published: 2023-05-18 - Granted: 2025-01-07 - Earliest claimed: 2020-08-20 - Assignees: Mediatek Inc.; National Taiwan University - Applicants: Mediatek Inc.; Chee-Wee Liu - Inventors: Ming-Tzong Yang; Hsien-Hsin Lin; Wen-Kai Wan; Chia-Che Chung; Chee-Wee Liu - Web page: https://patentgrep.com/patent/US12191226B2 ## CPC - H10D 86/215: {comprising FinFETs} - H10W 40/25: characterised by their materials - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/62: Fin field-effect transistors [FinFET] - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10W 20/01: {Manufacture or treatment} - H10W 40/259: {Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)} - H10D 30/6219: {characterised by the source or drain electrodes} - H10W 40/254: {Diamond} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device and method for forming same. According to an embodiment. The method provides a base substrate, forms a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm−1K−1 and 1200 Wm−1K−1. This method further forms a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor. The method further removes the base substrate. ## Claims ### Claim 1 A semiconductor device mounted on a substrate through solder bumps, comprising: a heat dissipation substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm−1K−1 and 1200 Wm−1K−1; and a device layer disposed on the heat dissipation substrate, wherein the device layer comprises a transistor, wherein the heat dissipation substrate is formed as a top layer of the semiconductor device and separated from the substrate by the device layer and the solder bumps, wherein the heat dissipation substrate has a bottommost surface located directly above all the solder bumps, and the bottommost surface of the heat dissipation substrate and a top surface of the device layer overlap each other completely. ### Claim 2 (depends on 1) The semiconductor device as claimed in claim 1, wherein the heat dissipation substrate comprises a dielectric material. ### Claim 3 (depends on 2) The semiconductor device as claimed in claim 2, wherein the dielectric material comprises BeO, BN, diamond, or a combination thereof. ### Claim 4 (depends on 1) The semiconductor device as claimed in claim 1, wherein a thickness of the heat dissipation substrate is between 75 μm and 150 μm. ### Claim 5 (depends on 1) The semiconductor device as claimed in claim 1, wherein the device layer is a silicon transistor layer. ### Claim 6 (depends on 5) The semiconductor device as claimed in claim 5, wherein the silicon transistor layer comprises a fin-like field effect transistor, a gate-all-around transistor, or a combination thereof. ### Claim 7 (depends on 1) The semiconductor device as claimed in claim 1, further comprising an interconnection layer disposed on the device layer. ### Claim 8 A method of forming a semiconductor device mounted on a substrate through solder bumps, comprising: providing a base substrate; forming a heat dissipation substrate on the base substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm−1K−1 and 1200 Wm−1K−1; forming a device layer on the heat dissipation substrate, wherein the device layer comprises a transistor; removing the base substrate; and soldering the semiconductor device to the substrate through the solder bumps, such that the heat dissipation substrate is formed as a top layer of the semiconductor device and located farther from the substrate than the device layer and the solder bumps, wherein the heat dissipation substrate has a bottommost surface located directly above all the solder bumps, and the bottommost surface of the heat dissipation substrate and a top surface of the device layer overlap each other completely. ### Claim 9 (depends on 8) The method as claimed in claim 8, wherein forming the heat dissipation substrate on the base substrate comprises performing a CVD process to form a dielectric material layer. ### Claim 10 (depends on 9) The method as claimed in claim 9, wherein the material of the dielectric material layer comprises BeO, BN, diamond, or a combination thereof. ### Claim 11 (depends on 8) The method as claimed in claim 8, wherein a thickness of the heat dissipation substrate is between 75 μm and 150 μm. ### Claim 12 (depends on 8) The method as claimed in claim 8, further comprising forming an interconnection layer on the device layer. ### Claim 13 (depends on 8) The method as claimed in claim 8, wherein removing the base substrate comprises performing a grinding process on the base substrate. ### Claim 14 (depends on 8) The method as claimed in claim 8, wherein the base substrate is completely removed after the grinding process. ### Claim 15 A method of forming a semiconductor device mounted on a substrate through solder bumps, comprising: providing a base substrate; forming a device layer on the base substrate, wherein the device layer comprises a transistor; removing the base substrate; attaching the device layer to a heat dissipation substrate, wherein a thermal conductivity of the heat dissipation substrate is between 200 Wm−1K−1 and 1200 Wm−1K−1; and soldering the semiconductor device to the substrate through the solder bumps, such that the heat dissipation substrate is formed as a top layer of the semiconductor device and located farther from the substrate than the device layer and the solder bumps, wherein the heat dissipation substrate has a bottommost surface located directly above all the solder bumps, and the bottommost surface of the heat dissipation substrate and a top surface of the device layer overlap each other completely. ### Claim 16 (depends on 15) The method as claimed in claim 15, wherein the heat dissipation substrate is formed of BeO, BN, diamond, or a combination thereof. ### Claim 17 (depends on 16) The method as claimed in claim 16, wherein removing the base substrate comprises: holding the device layer with a carrier; and performing a grinding process to remove the base substrate completely. ### Claim 18 (depends on 17) The method as claimed in claim 17, wherein the carrier holds the device layer while the device layer is being attached to the heat dissipation substrate.