# US 12,191,221 B2 · Semiconductor package

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- Number: US 12,191,221 B2
- Document ID: US12191221B2
- Status: Granted
- Kind: B2
- Application number: 17/677,459
- Filed: 2022-02-22
- Published: 2023-01-05
- Granted: 2025-01-07
- Earliest claimed: 2021-07-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yonghwan Kwon
- Web page: https://patentgrep.com/patent/US12191221B2

## CPC

- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 90/00: Package configurations
- H10P 72/7424: {used as a support during the manufacture of self-supporting substrates}
- H10P 72/7436: {used to support a device or a wafer when forming electrical connections thereto}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/6528: {of the portions that connect to chips, wafers or package parts}
- H10W 72/073: {of die-attach connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor package may include a redistribution substrate including first and second surfaces opposite each other, a first semiconductor chip on the first surface, a first molding portion on a side surface of the first semiconductor chip, a second semiconductor chip between the first semiconductor chip and the redistribution substrate, a second molding portion between the redistribution substrate and the first molding portion and on a side surface of the second semiconductor chip, bump patterns between the second semiconductor chip and the redistribution substrate, and a mold via penetrating the second molding portion and electrically connecting the first semiconductor chip to the redistribution substrate. The redistribution substrate may include first and second redistribution patterns sequentially in an insulating layer. The mold via may contact the second redistribution pattern, and the bump patterns may contact the first redistribution pattern.

## Claims

### Claim 1

A semiconductor package, comprising:
a redistribution substrate comprising a first surface and a second surface, which are opposite each other;
a first semiconductor chip on the first surface of the redistribution substrate;
a first molding portion on a side surface of the first semiconductor chip;
a second semiconductor chip between the first semiconductor chip and the redistribution substrate;
a second molding portion between the redistribution substrate and the first molding portion, the second molding portion on a side surface of the second semiconductor chip;
bump patterns between the second semiconductor chip and the redistribution substrate; and
a mold via penetrating the second molding portion and electrically connecting the first semiconductor chip to the redistribution substrate, wherein
the redistribution substrate comprises an insulating layer, a first redistribution pattern in the insulating layer, and a second redistribution pattern in the insulating layer,
the first redistribution pattern and the second redistribution pattern are sequentially stacked in a direction from the first surface of the redistribution substrate toward the second surface,
the mold via is in contact with the second redistribution pattern, and
the bump patterns are in contact with the first redistribution pattern.

### Claim 2 (depends on 1)

The semiconductor package of claim 1, wherein
the mold via comprises a wire portion and a via portion,
the wire portion is on the second molding portion; and
the via portion extends vertically and penetrates the second molding portion, and
a width of the via portion of the mold via increases in a direction from the first semiconductor chip toward the redistribution substrate.

### Claim 3 (depends on 1)

The semiconductor package of claim 1, further comprising:
a third semiconductor chip in the first molding portion and spaced apart from the first semiconductor chip,
wherein the second semiconductor chip is between the third semiconductor chip and the redistribution substrate.

### Claim 4 (depends on 1)

The semiconductor package of claim 1, wherein
the first semiconductor chip comprises an active surface and an inactive surface, which are opposite each other, and
the first molding portion is in contact with the inactive surface of the first semiconductor chip.

### Claim 5 (depends on 4)

The semiconductor package of claim 4, further comprising:
an adhesive layer between the first semiconductor chip and the second semiconductor chip,
wherein the adhesive layer is in contact with the active surface of the first semiconductor chip, and
a bottom surface of the adhesive layer is coplanar with a bottom surface of the second molding portion.

### Claim 6 (depends on 1)

The semiconductor package of claim 1, wherein a thermal expansion coefficient of the first molding portion and a thermal expansion coefficient of the second molding portion are different from each other.

### Claim 7 (depends on 1)

The semiconductor package of claim 1, wherein
the mold via comprises a seed pattern and a conductive pattern on the seed pattern,
the seed pattern is in contact with the second molding portion,
the seed pattern and the conductive pattern comprise a same metallic material, and
a density of the metallic material in the seed pattern is different from a density of the metallic material in the conductive pattern.

### Claim 8 (depends on 1)

The semiconductor package of claim 1, wherein
the first semiconductor chip comprises a chip pad, which is provided therein and contacts the mold via, and
a thickness of the chip pad ranges from 5 μm to 15 μm.

### Claim 9 (depends on 1)

The semiconductor package of claim 1, further comprising:
connection terminals on the second surface of the redistribution substrate,
wherein a pitch between the connection terminals is larger than a pitch between the bump patterns.

### Claim 10 (depends on 1)

The semiconductor package of claim 1, wherein a top surface of the second molding portion is at a level higher than a top surface of each of the bump patterns.

### Claim 11

A semiconductor package, comprising:
a redistribution substrate comprising a first surface and a second surface, which are opposite to each other;
a first semiconductor chip and a second semiconductor chip on the first surface of the redistribution substrate,
each of the first semiconductor chip and the second semiconductor chip comprising an active surface and an inactive surface, which are opposite each other;
a third semiconductor chip between the first semiconductor chip and the redistribution substrate and between the second semiconductor chip and the redistribution substrate;
a first molding portion on a side surface of each of the first semiconductor chip and the second semiconductor chip;
a second molding portion between the redistribution substrate and the first molding portion, the second molding portion on a side surface of the third semiconductor chip; and
a mold via penetrating the second molding portion and electrically connecting the redistribution substrate to the first semiconductor chip,
wherein a width of the mold via in the second molding portion increases in a direction from the first semiconductor chip toward the redistribution substrate, and
the first molding portion is in contact with the inactive surface of each of the first semiconductor chip and the second semiconductor chip.

### Claim 12 (depends on 11)

The semiconductor package of claim 11, wherein
the mold via comprises a seed pattern and a conductive pattern on the seed pattern,
the seed pattern is in contact with the second molding portion, and
the seed pattern and the conductive pattern comprise a same material.

### Claim 13 (depends on 11)

The semiconductor package of claim 11, wherein
the redistribution substrate comprises an insulating layer, a first redistribution pattern in the insulating layer, and a second redistribution pattern in the insulating layer,
the first redistribution pattern and the second redistribution pattern are sequentially stacked in a direction from the first surface of the redistribution substrate toward the second surface,
the first redistribution pattern comprises a seed pattern and a conductive pattern on the seed pattern, which is in contact with the second molding portion, and a conductive pattern, which is provided on the seed pattern, and
the seed pattern and the conductive pattern of the first redistribution pattern comprise a same material.

### Claim 14 (depends on 13)

The semiconductor package of claim 13, further comprising:
a bump pattern between the third semiconductor chip and the redistribution substrate,
wherein the mold via is in contact with the second redistribution pattern, and
the bump pattern is in contact with the first redistribution pattern.

### Claim 15 (depends on 11)

The semiconductor package of claim 11, wherein a thermal expansion coefficient of the first molding portion and a thermal expansion coefficient of the second molding portion are different from each other.

### Claim 16

A semiconductor package, comprising:
a redistribution substrate comprising a first surface and a second surface, which are opposite each other, wherein
the redistribution substrate includes an insulating layer, a first redistribution pattern in the insulating layer, a second redistribution pattern in the insulating layer, a third redistribution pattern in the insulating layer, and a bonding pad on the third redistribution pattern, and
the first redistribution pattern, the second redistribution pattern, and the third redistribution pattern are sequentially stacked in a direction from the first surface of the redistribution substrate toward the second surface;
a first semiconductor chip and a second semiconductor chip on the first surface of the redistribution substrate,
each of the first semiconductor chip and the second semiconductor chip comprising an active surface and an inactive surface, which are opposite to each other;
a first chip pad adjacent to the active surface of the first semiconductor chip;
a second chip pad adjacent to the active surface of the second semiconductor chip;
a first molding portion on a side surface and the inactive surface of each of the first semiconductor chip and the second semiconductor chip;
a third semiconductor chip between the first semiconductor chip and the redistribution substrate and between the second semiconductor chip and the redistribution substrate;
an adhesive layer between the first semiconductor chip and the third semiconductor chip and between the second semiconductor chip and the third semiconductor chip;
a second molding portion between the redistribution substrate and the first molding portion, the second molding portion being provided on a side surface of the third semiconductor chip and a top surface of the third semiconductor chip;
bump patterns between the redistribution substrate and the third semiconductor chip;
a mold via penetrating the second molding portion and electrically connecting the redistribution substrate to the first semiconductor chip; and
a connection terminal provided on the bonding pad, wherein
the mold via is in contact with the second redistribution pattern, and
the bump patterns are in contact with the first redistribution pattern.

### Claim 17 (depends on 16)

The semiconductor package of claim 16, wherein a thickness of the first chip pad ranges from 5 μm to 15 μm.

### Claim 18 (depends on 16)

The semiconductor package of claim 16, wherein a bottom surface of the adhesive layer is coplanar with a bottom surface of the second molding portion.

### Claim 19 (depends on 16)

The semiconductor package of claim 16, wherein
the mold via comprises a seed pattern and a conductive pattern on the seed pattern,
the mold via is in contact with the second molding portion,
the conductive pattern is on the seed pattern, and
the seed pattern and the conductive pattern comprise a same material.

### Claim 20 (depends on 16)

The semiconductor package of claim 16, wherein a top surface of the second molding portion is at a level higher than a top surface of each of the bump patterns.