# US 12,191,212 B2 · Semiconductor method and device

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- Number: US 12,191,212 B2
- Document ID: US12191212B2
- Status: Granted
- Kind: B2
- Application number: 17/737,766
- Filed: 2022-05-05
- Published: 2023-01-19
- Granted: 2025-01-07
- Earliest claimed: 2021-07-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yi-Cheng Li; Pin-Ju Liang; Ta-Chun Ma; Pei-Ren Jeng; Yee-Chia Yeo
- Web page: https://patentgrep.com/patent/US12191212B2

## CPC

- H10D 84/0167: {Manufacturing their channels}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 50/642: {Chemical etching}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a fin extending from a substrate; depositing a liner over a top surface and sidewalls of the fin, where the minimum thickness of the liner is dependent on selected according to a first germanium concentration of the fin; forming a shallow trench isolation (STI) region adjacent the fin; removing a first portion of the liner on sidewalls of the fin, the first portion of the liner being above a topmost surface of the STI region; and forming a gate stack on sidewalls and a top surface of the fin, where the gate stack is in physical contact with the liner.

## Claims

### Claim 1

A method comprising:
forming a fin extending from a substrate;
depositing a liner over a top surface and sidewalls of the fin, wherein a minimum thickness of the liner is selected according to a first germanium concentration of the fin;
forming a shallow trench isolation (STI) region adjacent the fin, wherein the fin comprises a first portion above a topmost surface of the STI region, and a second portion below the topmost surface of the STI region, wherein the first portion comprises silicon germanium and the second portion comprises silicon;
removing a first portion of the liner on the sidewalls of the fin, the first portion of the liner being above the topmost surface of the STI region; and
forming a gate stack on sidewalls and a top surface of the fin, wherein the gate stack is in physical contact with the liner.

### Claim 2 (depends on 1)

The method of claim 1, wherein the liner comprises silicon, and wherein the liner comprises a first thickness in a range from 0.5 nm to 5 nm.

### Claim 3 (depends on 1)

The method of claim 1, wherein depositing the liner takes place at a process temperature in a range from 350° C. to 500° C. and a process pressure in a range from 0.5 mtorr to 3 mtorr.

### Claim 4 (depends on 1)

The method of claim 1, further comprising etching sidewalls of the first portion of the fin.

### Claim 5 (depends on 1)

The method of claim 1, wherein a topmost point of the STI region is at a level between a level of a topmost surface of the liner and a level of a bottommost surface of the first portion of the fin.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first portion of the fin has a first width that is smaller than a second width of the second portion of the fin.

### Claim 7 (depends on 1)

The method of claim 1, wherein removing the first portion of the liner on the sidewalls of the fin comprises performing a wet etching process using ozone (O3) as an etchant.

### Claim 8

A method comprising:
patterning a substrate such that a semiconductor fin protrudes from a major surface of the substrate, wherein the semiconductor fin comprises a first portion and a second portion below the first portion, wherein a first material of the first portion of the semiconductor fin is different from a second material of the second portion of the semiconductor fin, wherein the first material comprises silicon germanium having a first germanium concentration that is in a range from 20 atomic percent to 80 atomic percent;
depositing a semiconductor liner over the substrate, along the first portion of the semiconductor fin, and along the second portion of the semiconductor fin;
depositing a dielectric material over the semiconductor liner, the substrate, and the semiconductor fin;
recessing the dielectric material to form a shallow trench isolation (STI) region adjacent the semiconductor fin, wherein after the recessing the first portion of the semiconductor fin protrudes above a top surface of the STI region; and
etching the semiconductor liner from sidewalls of the first portion of the semiconductor fin.

### Claim 9 (depends on 8)

The method of claim 8, wherein the second material is silicon.

### Claim 10 (depends on 8)

The method of claim 8, wherein the second portion of the semiconductor fin extends below the top surface of the STI region.

### Claim 11 (depends on 8)

The method of claim 8, wherein depositing the semiconductor liner comprises depositing a silicon layer that has a minimum thickness that is in a range from 0.5 nm to 5 nm at the thinnest point of the silicon layer in a cross-sectional view.

### Claim 12 (depends on 11)

The method of claim 11, wherein the minimum thickness is selected according to the first germanium concentration of the first portion of the semiconductor fin.

### Claim 13 (depends on 8)

The method of claim 8, wherein a first height of the STI region that is closer to a sidewall of the semiconductor liner is larger than a second height of the STI region that is further away from the sidewall of the semiconductor liner.

### Claim 14 (depends on 8)

The method of claim 8, wherein after etching the semiconductor liner from the sidewalls of the first portion of the semiconductor fin, the first portion of the semiconductor fin has a first width that is different from a second width of the second portion of the semiconductor fin.

### Claim 15 (depends on 14)

The method of claim 14, wherein the first width of the first portion of the semiconductor fin is smaller than the second width of the second portion of the semiconductor fin.

### Claim 16

A device comprising:
a semiconductor fin extending from a substrate, the semiconductor fin comprising:
a first portion; and
a second portion below the first portion, wherein the first portion comprises silicon germanium, and the second portion comprises silicon, wherein a germanium concentration of the first portion of the semiconductor fin is in a range from 20 atomic percent to 80 atomic percent;
a semiconductor liner on sidewalls of the second portion of the semiconductor fin; and
a shallow trench isolation (STI) region adjacent the semiconductor fin, wherein a topmost point of the STI region is at a level that is between a level of a topmost surface of the semiconductor liner and a level of a bottommost surface of the first portion of the semiconductor fin.

### Claim 17 (depends on 15)

The device of claim 15, wherein a sum of a first width of the second portion of the semiconductor fin, a second width of the semiconductor liner on a first sidewall of the second portion of the semiconductor fin, and a third width of the semiconductor liner on a second sidewall of the second portion of the semiconductor fin is in a range from 6 nm to 15 nm.

### Claim 18 (depends on 17)

The device of claim 17, wherein the first width of the second portion of the semiconductor fin is larger than a fourth width of the first portion of the semiconductor fin.

### Claim 19 (depends on 15)

The device of claim 15, wherein the semiconductor liner comprises silicon.

### Claim 20 (depends on 15)

The device of claim 15, wherein the topmost point of the STI region and a bottommost surface of the STI region are in physical contact with the semiconductor liner.