# US 12,191,211 B2 · Method for making semiconductor device using a stress memorization technique

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- Number: US 12,191,211 B2
- Document ID: US12191211B2
- Status: Granted
- Kind: B2
- Application number: 17/752,869
- Filed: 2022-05-25
- Published: 2023-11-02
- Granted: 2025-01-07
- Earliest claimed: 2022-04-29
- Assignees: United Semiconductor (Xiamen) Co., Ltd.
- Applicants: United Semiconductor (Xiamen) Co., Ltd.
- Inventors: Linshan Yuan; Guang Yang; Yuchun Guo; Jinjian Ouyang; Chin-Chun Huang; Wen Yi Tan
- Web page: https://patentgrep.com/patent/US12191211B2

## CPC

- H10D 30/796: {having memorised stress for introducing strain in the channel regions, e.g. recrystallised polysilicon gates}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating a semiconductor device is disclosed. A substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor is provided. A stress memorization technique (SMT) process is performed. The SMT process includes steps of depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process. A lithographic process and an etching process are performed to form a patterned SMT film. A silicide layer is formed on the MOS transistor. The patterned SMT film acts as a salicide block layer when forming the silicide layer.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a substrate having thereon at least one metal-oxide-semiconductor (MOS) transistor;
performing a stress memorization technique (SMT) process comprising depositing an SMT film covering the at least one MOS transistor on the substrate, and subjecting the SMT film to a thermal process;
after the SMT process, performing a lithographic process and an etching process to form a patterned SMT film; and
forming a silicide layer on the MOS transistor, wherein the patterned SMT film acts as a salicide block layer when forming the silicide layer.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the at least one MOS transistor is an NMOS transistor.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the SMT film comprises a silicon oxide layer and a silicon nitride layer.

### Claim 4 (depends on 3)

The method according to claim 3, wherein the silicon nitride layer is a stressed silicon nitride layer.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the patterned SMT film covers a non-silicide region on the substrate that does not need to form a silicide layer.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the thermal process comprises a rapid thermal process.

### Claim 7 (depends on 1)

The method according to claim 1, wherein the thermal process comprises a laser annealing process.