# US 12,191,209 B2 · Semiconductor device

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- Number: US 12,191,209 B2
- Document ID: US12191209B2
- Status: Granted
- Kind: B2
- Application number: 18/297,952
- Filed: 2023-04-10
- Published: 2023-08-03
- Granted: 2025-01-07
- Earliest claimed: 2019-03-14
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Chiang; Chung-Wei Hsu; Lung-Kun Chu; Jia-Ni Yu; Chih-Hao Wang; Mao-Lin Huang
- Web page: https://patentgrep.com/patent/US12191209B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/0243: {using dummy structures having essentially the same shapes as the semiconductor bodies, e.g. to provide stability}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 84/853: {comprising FinFETs}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 10/0145: {of trenches having shapes other than rectangular or V-shape (H10W10/0143 takes precedence)}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/364: {of IGFETs}
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanostructures formed over a substrate, and a first S/D structure formed on sidewall surfaces of the first semiconductor nanostructures. The semiconductor device includes a plurality of second semiconductor nanostructures formed over the substrate, and a second S/D structure formed on sidewall surfaces of the second semiconductor nanostructures. The semiconductor device includes an isolation structure formed between the first S/D structure and the second S/D structure, and the isolation structure has a first sidewall surface in direct contact with the first S/D structure and a second sidewall surface in direct contact with the second S/D structure.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of first semiconductor nanostructures formed along a first direction over a substrate;
a first S/D structure and a second S/D structure formed on opposite sidewall surfaces of the first semiconductor nanostructures along the first direction;
a plurality of second semiconductor nanostructures formed over the substrate;
a third S/D structure and a fourth S/D structure formed on opposite sidewall surfaces of the second semiconductor nanostructures along the first direction;
an isolation structure formed between the first S/D structure and the third S/D structure, wherein the isolation structure has a first sidewall surface facing the first S/D structure and a second sidewall surface facing the third S/D structure, and the isolation structure is separate from the first semiconductor nanostructures by the first S/D structure,
wherein the isolation structure is formed along the first direction, and the first S/D structure is separated from the third S/D structure by the isolation structure.

### Claim 2 (depends on 1)

The semiconductor device as claimed in claim 1, wherein a top surface of the isolation structure is lower than a top surface of the first S/D structure.

### Claim 3 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
an etch stop layer formed on the first S/D structure and the second S/D structure, wherein a portion of the etch stop layer is lower than a bottommost first semiconductor nanostructure.

### Claim 4 (depends on 3)

The semiconductor device as claimed in claim 3, further comprising:
a dielectric layer formed on the etch stop layer, wherein a portion of the dielectric layer is lower than a top surface of the isolation structure.

### Claim 5 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a gate dielectric layer formed on the first semiconductor nanostructures, the second semiconductor nanostructures and the isolation structure.

### Claim 6 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a p-type work function layer surrounding each of the first semiconductor nanostructures, wherein the p-type work function layer has a sidewall surface between the first semiconductor nanostructures and the isolation structure.

### Claim 7 (depends on 6)

The semiconductor device as claimed in claim 6, further comprising:
a n-type work function layer formed over the p-type work function layer and on the second semiconductor nanostructures, wherein the n-type work function layer has a step height located between the first semiconductor nanostructures and the isolation structure.

### Claim 8 (depends on 6)

The semiconductor device as claimed in claim 6, wherein the p-type work function layer does not surround the second semiconductor nanostructures.

### Claim 9 (depends on 1)

The semiconductor device as claimed in claim 1, further comprising:
a first hard mask layer formed over the first semiconductor nanostructures, wherein the first hard mask layer is in direct contact with the first S/D structure.

### Claim 10

A semiconductor device, comprising:
a plurality of first semiconductor nanostructures formed over a substrate;
a first hard mask layer formed over the first semiconductor nanostructures, wherein a bottommost surface of the first hard mask layer is higher than a topmost surface of the first semiconductor nanostructures;
a plurality of second semiconductor nanostructures formed over the substrate;
a second hard mask layer formed over the second semiconductor nanostructures;
a gate dielectric layer surrounding the first semiconductor nanostructures and the second semiconductor nanostructures, wherein the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer; and
an isolation structure extending upwardly above the surface, wherein a top surface of the isolation structure is higher than a topmost first semiconductor nanostructure.

### Claim 11 (depends on 10)

The semiconductor device as claimed in claim 10, wherein the first hard mask layer is in direct contact with the gate dielectric layer.

### Claim 12 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising:
a p-type work function layer surrounding each of the first semiconductor nanostructures, wherein the p-type work function layer is between the first hard mask layer and a topmost first semiconductor nanostructure.

### Claim 13 (depends on 12)

The semiconductor device as claimed in claim 12, further comprising:
a n-type work function layer formed over the p-type work function layer and on the second semiconductor nanostructures, wherein the n-type work function layer has a step height located between the first semiconductor nanostructures and an isolation structure.

### Claim 14 (depends on 10)

The semiconductor device as claimed in claim 10, further comprising:
a STI structure formed over the substrate wherein a portion of the isolation structure embedded in the STI structure.

### Claim 15 (depends on 14)

The semiconductor device as claimed in claim 14, wherein a top surface of the first hard mask layer is higher than a top surface of the isolation structure.

### Claim 16 (depends on 14)

The semiconductor device as claimed in claim 14, wherein the isolation structure has a top surface and a bottom surface, and a top width of the top surface is smaller than a bottom width of the bottom surface of the isolation structure.

### Claim 17

A semiconductor device, comprising:
a STI structure formed over a substrate;
a plurality of first semiconductor nanostructures formed over a first fin base over the substrate, wherein the first semiconductor nanostructures are directly over the first fin base;
a plurality of second semiconductor nanostructures formed over the substrate;
a gate metal fill formed over the first semiconductor nanostructures and the second semiconductor nanostructures; and
an isolation structure between the first semiconductor nanostructures and the second semiconductor nanostructures, wherein a bottom portion of the isolation structure is lower than a top surface of the STI structure.

### Claim 18 (depends on 17)

The semiconductor device as claimed in claim 17, further comprising:
a p-type work function layer surrounding each of the first semiconductor nanostructures, wherein the p-type work function layer is between the isolation structure and a topmost first semiconductor nanostructure.

### Claim 19 (depends on 18)

The semiconductor device as claimed in claim 18, further comprising:
a n-type work function layer formed over the p-type work function layer and on the second semiconductor nanostructures, wherein the n-type work function layer has a step height located between the first semiconductor nanostructures and the isolation structure.

### Claim 20 (depends on 17)

The semiconductor device as claimed in claim 17, further comprising:
a gate spacer adjacent to the gate metal fill; and
an etch stop layer formed adjacent to the gate spacer, wherein a portion of the etch stop layer is in direct contact with the isolation structure.