# US 12,191,208 B2 · Dual strained semiconductor substrate and patterning

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- Number: US 12,191,208 B2
- Document ID: US12191208B2
- Status: Granted
- Kind: B2
- Application number: 17/482,573
- Filed: 2021-09-23
- Published: 2023-03-23
- Granted: 2025-01-07
- Earliest claimed: 2021-09-23
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Kangguo Cheng; Shogo Mochizuki; Juntao Li
- Web page: https://patentgrep.com/patent/US12191208B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/791: {Arrangements for exerting mechanical stress on the crystal lattice of the channel regions}
- H10D 62/121: {oriented parallel to substrates}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 84/851: {comprising IGFETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A dielectric layer is on top of a first semiconductor stack. The first semiconductor stack is compressively strained. A second semiconductor stack is on top of the dielectric layer. The second semiconductor stack is tensely strained.

## Claims

### Claim 1

A semiconductor structure comprising:
a dielectric layer on top of a first semiconductor stack, wherein the first semiconductor stack is compressively strained, and wherein the first semiconductor stack comprises Silicon Germanium (SiGe); and
a second semiconductor stack on top of the dielectric layer, wherein the second semiconductor stack is tensely strained.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the second semiconductor stack comprises Silicon.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the first semiconductor stack comprises two or more alternating layers of Silicon Germanium (SiGe) and a substrate.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the second semiconductor stack comprises two or more alternating layers of a Silicon Germanium (SiGe) layer and a Silicon layer.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein a first liner is located between and in contact with the dielectric layer and the first semiconductor stack and wherein a second liner is located between and in contact with the dielectric layer and the second semiconductor stack.

### Claim 6

A semiconductor structure comprising:
a first silicon germanium (SiGe) layer on top of and in contact with a substrate;
a first liner layer on top of and in contact with the first SiGe layer;
a first dielectric layer on top of and in contact with the first liner layer;
a second liner layer on top of and in contact with the first dielectric layer;
a second dielectric layer on top of and in contact with the second liner layer; and
a second silicon germanium (SiGe) layer on top of and in contact with the second dielectric layer.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, further comprising:
a third dielectric layer surrounding and in contact with at least a portion of the substrate.

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, wherein the first SiGe layer is compressively strained.

### Claim 9 (depends on 6)

The semiconductor structure of claim 6, wherein the second SiGe layer is relaxed.

### Claim 10 (depends on 6)

The semiconductor structure of claim 6, wherein the first SiGe layer is 25% Germanium.