# US 12,191,207 B2 · Non-planar I/O and logic semiconductor devices having different workfunction on common substrate

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- Number: US 12,191,207 B2
- Document ID: US12191207B2
- Status: Granted
- Kind: B2
- Application number: 18/378,983
- Filed: 2023-10-11
- Published: 2024-02-01
- Granted: 2025-01-07
- Earliest claimed: 2019-01-22
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Roman W. Olac-Vaw; Walid M. Hafez; Chia-Hong Jan; Pei-Chi Liu
- Web page: https://patentgrep.com/patent/US12191207B2

## CPC

- H10D 84/014: {the gate conductors having different materials or different implants}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors}
- H10D 84/834: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.

## Claims

### Claim 1

An integrated circuit structure, comprising:
a first N-type device having a three-dimensional architecture, the first N-type device having a first three-dimensional body, the first three-dimensional body having a sidewall at an end of the three-dimensional body, and the first N-type device comprising a first gate electrode over the end of the first three-dimensional body and adjacent to the sidewall of the first three-dimensional body, and a second gate electrode over the first three-dimensional body and spaced apart from the first gate electrode, wherein the second gate electrode has a first gate length; and
a second N-type device having a three-dimensional architecture, the second N-type device having a second three-dimensional body, and the second N-type device comprising a third gate electrode over the second three-dimensional body, wherein the third gate electrode has a second gate length different than the first gate length, and wherein the third gate electrode has a workfunction layer having a thickness different than a thickness of a workfunction layer of the second gate electrode.

### Claim 2 (depends on 1)

The integrated circuit structure of claim 1, wherein the second gate length is less than the first gate length.

### Claim 3 (depends on 1)

The integrated circuit structure of claim 1, wherein the thickness of the workfunction layer of the third gate electrode is less than the thickness of the workfunction layer of the second gate electrode.

### Claim 4 (depends on 1)

The integrated circuit structure of claim 1, wherein the first N-type device is a logic transistor, and the second N-type device is an I/O transistor.

### Claim 5 (depends on 1)

The integrated circuit structure of claim 1, further comprising:
a first gate dielectric between the first three-dimensional body and the first gate electrode;
a second gate dielectric between the first three-dimensional body and the second gate electrode; and
a third gate dielectric between the second three-dimensional body and the third gate electrode.

### Claim 6 (depends on 1)

The integrated circuit structure of claim 1, further comprising a fourth gate electrode over an end of the second three-dimensional body and adjacent to a sidewall of the second three-dimensional body.

### Claim 7

An integrated circuit structure, comprising:
a first P-type device having a three-dimensional architecture, the first P-type device having a first three-dimensional body, the first three-dimensional body having a sidewall at an end of the three-dimensional body, and the first P-type device comprising a first gate electrode over the end of the first three-dimensional body and adjacent to the sidewall of the first three-dimensional body, and a second gate electrode over the first three-dimensional body and spaced apart from the first gate electrode, wherein the second gate electrode has a first gate length; and
a second P-type device having a three-dimensional architecture, the second P-type device having a second three-dimensional body, and the second P-type device comprising a third gate electrode over the second three-dimensional body, wherein the third gate electrode has a second gate length different than the first gate length, and wherein the third gate electrode has a workfunction layer having a thickness different than a thickness of a workfunction layer of the second gate electrode.

### Claim 8 (depends on 7)

The integrated circuit structure of claim 7, wherein the second gate length is less than the first gate length.

### Claim 9 (depends on 7)

The integrated circuit structure of claim 7, wherein the thickness of the workfunction layer of the third gate electrode is less than the thickness of the workfunction layer of the second gate electrode.

### Claim 10 (depends on 7)

The integrated circuit structure of claim 7, wherein the first P-type device is a logic transistor, and the second P-type device is an I/O transistor.

### Claim 11 (depends on 7)

The integrated circuit structure of claim 7, further comprising:
a first gate dielectric between the first three-dimensional body and the first gate electrode;
a second gate dielectric between the first three-dimensional body and the second gate electrode; and
a third gate dielectric between the second three-dimensional body and the third gate electrode.

### Claim 12 (depends on 7)

The integrated circuit structure of claim 7, further comprising a fourth gate electrode over an end of the second three-dimensional body and adjacent to a sidewall of the second three-dimensional body.

### Claim 13

A computing system, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first device having a three-dimensional architecture, the first device of a conductivity type, the first device having a first three-dimensional body, the first three-dimensional body having a sidewall at an end of the three-dimensional body, and the first device comprising a first gate electrode over the end of the first three-dimensional body and adjacent to the sidewall of the first three-dimensional body, and a second gate electrode over the first three-dimensional body and spaced apart from the first gate electrode, wherein the second gate electrode has a first gate length; and
a second device having a three-dimensional architecture, the second device of the conductivity type, the second device having a second three-dimensional body, and the second device comprising a third gate electrode over the second three-dimensional body, wherein the third gate electrode has a second gate length different than the first gate length, and wherein the third gate electrode has a workfunction layer having a thickness different than a thickness of a workfunction layer of the second gate electrode.

### Claim 14 (depends on 13)

The computing system of claim 13, wherein the conductivity type is N-type.

### Claim 15 (depends on 13)

The computing system of claim 13, wherein the conductivity type is P-type.

### Claim 16 (depends on 13)

The computing system of claim 13, further comprising:
a memory coupled to the board.

### Claim 17 (depends on 13)

The computing system of claim 13, further comprising:
a communication chip coupled to the board.

### Claim 18 (depends on 13)

The computing system of claim 13, further comprising:
a camera coupled to the board.

### Claim 19 (depends on 13)

The computing system of claim 13, further comprising:
a battery coupled to the board.

### Claim 20 (depends on 13)

The computing system of claim 13, wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.