# US 12,191,206 B2 · Method of manufacturing fin spacers having different heights using a polymer-generating etching process

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- Number: US 12,191,206 B2
- Document ID: US12191206B2
- Status: Granted
- Kind: B2
- Application number: 17/353,213
- Filed: 2021-06-21
- Published: 2021-10-07
- Granted: 2025-01-07
- Earliest claimed: 2018-07-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Lien Huang
- Web page: https://patentgrep.com/patent/US12191206B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10P 14/6349: {Deposition of epitaxial materials}
- H10P 50/283: {by chemical means}
- H10W 10/011: {of isolation regions comprising dielectric materials}
- H10W 10/10: Isolation regions comprising dielectric materials
- H10D 30/0212: {using self-aligned silicidation}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a gate stack on a plurality of semiconductor fins. The plurality of semiconductor fins includes a plurality of inner fins, and a first outer fin and a second outer fin on opposite sides of the plurality of inner fins. Epitaxy regions are grown based on the plurality of semiconductor fins, and a first height of the epitaxy regions measured along an outer sidewall of the first outer fin is smaller than a second height of the epitaxy regions measured along an inner sidewall of the first outer fin.

## Claims

### Claim 1

A method comprising:
forming isolation regions over a bulk semiconductor substrate;
recessing the isolation regions, wherein top portions of semiconductor strips between the isolation regions protrude higher than top surfaces of the isolation regions to form a fin group comprising a plurality of fins, and wherein the plurality of fins comprise:
a plurality of inner fins; and
a first outer fin and a second outer fin on opposite sides of the plurality of inner fins;
forming fin spacers on sidewalls of the plurality of fins, wherein the fin spacers comprise inner fin spacers, and outer fin spacers having greater heights than the inner fin spacers, and wherein the forming the fin spacers comprises:
depositing a spacer layer on the plurality of fins; and
performing a first etching process on the spacer layer, wherein in the first etching process, a first polymer layer is generated on the spacer layer; and
removing the first polymer layer, wherein at a time after the first polymer layer is removed, the spacer layer comprises thinned portions covering top surfaces of the plurality of fins.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, after the first polymer layer is removed, performing a second etching process on the spacer layer, wherein in the second etching process, a second polymer layer is generated on the spacer layer.

### Claim 3 (depends on 2)

The method of claim 2, further comprising, after the second etching process, removing the second polymer layer, wherein after the second polymer layer is removed, the top surfaces of the plurality of fins are exposed.

### Claim 4 (depends on 1)

The method of claim 1, wherein first heights of the outer fin spacers are greater than second heights of the inner fin spacers by a height difference greater than about 2 nm.

### Claim 5 (depends on 1)

The method of claim 1, further comprising forming a gate spacer on sidewalls of a gate stack, wherein the gate spacer and the fin spacers are formed in common formation processes.

### Claim 6 (depends on 1)

The method of claim 1, wherein the first etching process is performed by generating plasma using a main power, and wherein in the first etching process, the main power is pulsed.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first etching process is performed by applying a bias power, and wherein in the first etching process, the bias power is pulsed.

### Claim 8 (depends on 7)

The method of claim 7, wherein the bias power is pulsed with a duty cycle in a range between about 10 percent and about 90 percent.

### Claim 9 (depends on 1)

The method of claim 1, further comprising epitaxially growing epitaxy regions based on the plurality of fins, wherein the epitaxially growing comprises pulsing a bias voltage with a plurality of cycles.

### Claim 10

A method comprising:
forming isolation regions extending into a semiconductor substrate;
forming a plurality of semiconductor fins protruding higher than the isolation regions, wherein the plurality of semiconductor fins comprise:
a first outer fin and a second outer fin; and
an inner fin between the first outer fin and the second outer fin;
depositing a spacer layer on top surfaces and sidewalls of the plurality of semiconductor fins;
forming fin spacers comprising outer fin spacers and inner fin spacers from the spacer layer, wherein the outer fin spacers on outer sidewalls of the first outer fin and the second outer fin are higher than the inner fin spacers on sidewalls of the inner fin, and wherein the forming the fin spacers comprises:
performing a first etching process to thin the spacer layer, wherein the first etching process comprises applying an etching chemical to be in contact with the spacer layer;
after the spacer layer is thinned, removing a first polymer layer generated in the first etching process, wherein the first polymer layer starts to be generated at a time after the etching chemical has been in contact with the spacer layer; and
epitaxially growing epitaxy regions based on the plurality of semiconductor fins.

### Claim 11 (depends on 10)

The method of claim 10, wherein after the first polymer layer is removed, remaining portions of the spacer layer overlap, and are directly on the top surfaces of, the plurality of semiconductor fins.

### Claim 12 (depends on 11)

The method of claim 11, wherein the spacer layer is thinned by the first etching process, and wherein at a time after the first polymer layer is removed, the spacer layer comprises portions overlapping the plurality of protruding fins.

### Claim 13 (depends on 10)

The method of claim 10, wherein in the first etching process, an upper portion of the spacer layer on the first outer fin is thinned more than a corresponding lower portion of the spacer layer on the first outer fin.

### Claim 14 (depends on 10)

The method of claim 10, further comprising, after the first polymer layer is removed, performing at least one cycle comprising:
performing a second etching process to thin a portion of the spacer layer that has been thinned in the first etching process; and
after the second etching process, removing a second polymer generated in the second etching process.

### Claim 15 (depends on 10)

The method of claim 10, wherein the fin spacers further comprise an additional inner fin spacer on the first outer fin and facing the inner fin, and wherein the additional inner fin spacer is shorter than the outer fin spacers.

### Claim 16 (depends on 15)

The method of claim 15, wherein the outer fin spacers are higher than the inner fin spacers by a height difference greater than about 2 nm.

### Claim 17

A method comprising:
depositing a spacer layer on top surfaces and sidewalls of a plurality of protruding fins, wherein the plurality of protruding fins comprise:
a first outer fin and a second outer fin; and
an inner fin between the first outer fin and the second outer fin;
etching the spacer layer to form fin spacers on sidewalls of the plurality of protruding fins, wherein the fin spacers comprise:
a first fin spacer on an outer sidewall of the first outer fin, wherein the first fin spacer has a first height; and
a second fin spacer on an inner sidewall of the first outer fin, wherein the second fin spacer has a second height smaller than the first height, and wherein the etching the spacer layer comprises performing a cycle comprising:
performing an etching process to etch the spacer layer, wherein a polymer layer is generated at a same time the spacer layer is etched, and is generated as a by-product of the etching process; and
after the etching process, removing the polymer layer generated in the etching process.

### Claim 18 (depends on 17)

The method of claim 17, wherein after the cycle is finished, the spacer layer still covers the first outer fin.

### Claim 19 (depends on 17)

The method of claim 17, wherein after the cycle is finished, the spacer layer still covers the inner fin.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
performing an additional etching process to further etch the spacer layer; and
after the etching process, removing an additional polymer layer generated in the additional etching process.