# US 12,191,205 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,191,205 B2
- Document ID: US12191205B2
- Status: Granted
- Kind: B2
- Application number: 17/685,845
- Filed: 2022-03-03
- Published: 2023-01-12
- Granted: 2025-01-07
- Earliest claimed: 2021-07-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University
- Inventors: Minghwei Hong; Juei-Nai Kwo; Tun-Wen Pi; Hsien-Wen Wan; Yi-Ting Cheng; Yu-Jie Hong
- Web page: https://patentgrep.com/patent/US12191205B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 62/118: {Nanostructure semiconductor bodies}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/685: {being perpendicular to the channel plane}
- H10D 84/0128: {Manufacturing their channels}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/364: {of IGFETs}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES

## Abstract

A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.

## Claims

### Claim 1

A method comprising:
forming a semiconductive channel layer on a substrate;
forming a dummy gate on the semiconductive channel layer;
forming gate spacers on opposite sides of the dummy gate;
removing the dummy gate to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench;
depositing a semiconductive protection layer in the gate trench and on the semiconductive channel layer;
oxidizing a top portion of the semiconductive protection layer to form an oxidation layer over a remaining portion of the semiconductive protection layer;
after oxidizing the top portion of the semiconductive protection layer, annealing the oxidation layer; and
after annealing the oxidation layer, forming a gate structure over the semiconductive protection layer and in the gate trench.

### Claim 2 (depends on 1)

The method of claim 1, further comprising removing the oxidation layer after annealing the oxidation layer and prior to forming the gate structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein the semiconductive protection layer is substantially free of germanium.

### Claim 4 (depends on 1)

The method of claim 1, wherein the semiconductive channel layer comprises germanium.

### Claim 5 (depends on 1)

The method of claim 1, wherein oxidizing the top portion of the semiconductive protection layer and annealing the oxidation layer are performed with no vacuum break therebetween.

### Claim 6 (depends on 1)

The method of claim 1, wherein oxidizing the top portion of the semiconductive protection layer comprises:
providing oxygen-containing gases onto the semiconductive protection layer; and
adjusting a flow rate of the oxygen-containing gases.

### Claim 7 (depends on 1)

The method of claim 1, wherein annealing the oxidation layer is such that an amount of GeOx in the oxidation layer is reduced while an amount of SiOx in the oxidation layer is increased.

### Claim 8 (depends on 1)

The method of claim 1, wherein annealing the oxidation layer is performed in a vacuum environment.

### Claim 9

A method comprising:
depositing a Ge-containing channel layer over a substrate;
depositing a semiconductive protection layer over the Ge-containing channel layer, wherein a germanium atomic percentage of the semiconductive protection layer is lower than a germanium atomic percentage of the Ge-containing channel layer;
performing an oxidation process on the semiconductive protection layer at a first temperature to form germanium oxide in a top portion of the semiconductive protection layer;
removing the germanium oxide at a second temperature higher than the first temperature; and
forming a gate structure over the semiconductive protection layer after removing the germanium oxide.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second temperature is lower than a temperature that breaks Si—O bonds.

### Claim 11 (depends on 9)

The method of claim 9, wherein the semiconductive protection layer has a thickness in a range of about 1 angstrom to about 30 angstrom.

### Claim 12 (depends on 9)

The method of claim 9, wherein the first temperature is room temperature.

### Claim 13 (depends on 9)

The method of claim 9, wherein a germanium atomic percentage of the semiconductive protection layer is lower than about 20 percent.

### Claim 14 (depends on 9)

The method of claim 9, wherein the Ge-containing channel layer is thicker than the semiconductive protection layer.

### Claim 15

A method comprising:
depositing a channel layer over a substrate;
depositing a semiconductive protection layer over the channel layer, wherein a germanium atomic percentage of the channel layer is higher than a germanium atomic percentage of the semiconductive protection layer;
performing an oxidation process to the semiconductive protection layer in an oxygen-containing environment;
performing an annealing process to the semiconductive protection layer after performing the oxidation process in an oxygen-free environment;
repeatedly performing the oxidation process and performing the annealing process; and
forming a gate structure over the semiconductive protection layer after repeatedly performing the oxidation process and performing the annealing process.

### Claim 16 (depends on 15)

The method of claim 15, wherein the annealing process is performed in a vacuum environment.

### Claim 17 (depends on 15)

The method of claim 15, wherein an annealing temperature of the annealing process is in a range of about 100° C. to about 1000° C.

### Claim 18 (depends on 15)

The method of claim 15, wherein the oxygen-containing environment comprises pure oxygen gases.

### Claim 19 (depends on 18)

The method of claim 18, wherein a flow rate of the pure oxygen gases is in a range of about 1 langmuir to about 1000 langmuir.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
removing an oxidation layer on the semiconductive protection layer prior the forming the gate structure, wherein the oxidation layer is formed during the oxidation process.