# US 12,191,202 B2 · Contact openings in semiconductor devices

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- Number: US 12,191,202 B2
- Document ID: US12191202B2
- Status: Granted
- Kind: B2
- Application number: 17/321,041
- Filed: 2021-05-14
- Published: 2021-11-18
- Granted: 2025-01-07
- Earliest claimed: 2020-05-15
- Assignees: Tokyo Electron Limited
- Applicants: Tokyo Electron Limited
- Inventors: Blaze Messer; Andrew Metz
- Web page: https://patentgrep.com/patent/US12191202B2

## CPC

- H10P 50/283: {by chemical means}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H01J 37/32: Gas-filled discharge tubes (heating by discharge H05B)
- H10P 50/267: {using plasmas}
- H10P 50/285: {of materials not containing Si, e.g. PZT or Al2O3}
- H10P 72/0421: {for drying etching}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/076: {in via holes or trenches}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10W 20/0765: {the thin functional dielectric layers being temporary, e.g. sacrificial layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)

## Abstract

In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a nitride etch stop layer aligned to a gate electrode and a metal-based etch stop layer aligned to a source/drain contact region. The method further includes selectively etching the metal-based etch stop layer, to remove the metal-based etch stop layer and expose a surface of the source/drain contact region, by exposing the semiconductor substrate to a plasma formed in a gas comprising a corrosive material and fluorocarbon.

## Claims

### Claim 1

A method, comprising:
receiving a semiconductor substrate that comprises:
a nitride etch stop layer over a gate electrode;
a metal-based etch stop layer over a source/drain contact region, the source/drain contact region being adjacent to the gate electrode, the gate electrode being to a first side of the source/drain contact region, the metal-based etch stop layer covering a surface of the source/drain contact region over an entire span of the surface between the gate electrode to the first side of the source/drain contact region and another gate electrode adjacent to a second side of the source/drain contact region; and
a dielectric layer overlying the metal-based etch stop layer and the nitride etch stop layer;
patterning, to expose respective surfaces of the metal-based etch stop layer and the nitride etch stop layer, the dielectric layer using a patterned resist layer over the dielectric layer as an etch mask; and
etching the metal-based etch stop layer using a plasma etching process that selectively etches the metal-based etch stop layer until the surface of the source/drain contact region is exposed, at least a portion of the nitride etch stop layer remaining over the gate electrode after the plasma etching process, the plasma etching process comprising exposing the semiconductor substrate to a plasma comprising a corrosive material and a fluorine-based reducing agent, wherein the corrosive material comprises chlorine and the fluorine-based reducing agent comprises fluorocarbon.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
the metal-based etch stop layer comprises titanium oxide, aluminum oxide, or titanium nitride; and
the nitride etch stop layer comprises silicon nitride.

### Claim 3 (depends on 1)

The method of claim 1, wherein the plasma etching process forms a passivation layer on the nitride etch stop layer, the passivation layer inhibiting etching of the nitride etch stop layer during the plasma etching process.

### Claim 4 (depends on 1)

The method of claim 1, wherein:
the nitride etch stop layer comprises silicon nitride; and
the metal-based etch stop layer comprises titanium oxide.

### Claim 5 (depends on 1)

The method of claim 1, wherein the plasma etching process comprises a single, continuous etch step to selectively etch the metal-based etch stop layer until the surface of the source/drain contact region is exposed.

### Claim 6 (depends on 1)

The method of claim 1, wherein the plasma etching process comprises a multi-step etch process that includes cyclically executing the following steps until the surface of the source/drain contact region is exposed:
forming a passivation layer on the surface of the nitride etch stop layer; and
etching a portion of the metal-based etch stop layer, the passivation layer inhibiting etching of the nitride etch stop layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
the surface of the nitride etch stop layer is a portion of a top surface of the nitride etch stop layer; and
the surface of the metal-based etch stop layer is an entirety of a top surface of the metal-based etch stop layer.

### Claim 8 (depends on 1)

The method of claim 1, wherein:
the semiconductor substrate further comprises a spacer separating the gate electrode and the nitride etch stop layer from the source/drain contact region and the metal-based etch stop layer; and
patterning the dielectric layer using the patterned resist layer over the dielectric layer as the etch mask exposes a surface of the spacer.

### Claim 9 (depends on 1)

The method of claim 1, further comprising depositing, after exposing the surface of the source/drain contact region, a metal to physically contact the source/drain contact region.

### Claim 10 (depends on 1)

The method of claim 1, wherein:
the plasma further comprises methane (CH4); and
during the plasma etching process, the methane causes a passivation layer to form on the dielectric layer overlying the metal-based etch stop layer and the nitride etch stop layer, the passivation layer inhibiting etching of the dielectric layer during the plasma etching process.

### Claim 11

A method, comprising:
receiving a semiconductor substrate that comprises a nitride etch stop layer aligned to a gate electrode and a metal-based etch stop layer aligned to a source/drain contact region; and
selectively etching the metal-based etch stop layer, to remove the metal-based etch stop layer and expose a surface of the source/drain contact region, by exposing the semiconductor substrate to a plasma formed in a gas comprising a corrosive material and fluorocarbon, wherein exposing the semiconductor substrate to the plasma formed in a gas comprising the corrosive material and the fluorocarbon facilitates forming a passivation layer on the nitride etch stop layer, the passivation layer inhibiting etching of the nitride etch stop layer during the plasma etching process while exposing the semiconductor substrate to the plasma formed in the gas comprising the corrosive material and the fluorocarbon.

### Claim 12 (depends on 11)

The method of claim 11, wherein the corrosive material comprises chlorine.

### Claim 13 (depends on 11)

The method of claim 11, wherein:
the metal-based etch stop layer comprises titanium oxide, aluminum oxide, or titanium nitride; and
the nitride etch stop layer comprises silicon nitride.

### Claim 14 (depends on 11)

The method of claim 11, wherein selectively etching the metal-based etch stop layer, to remove the metal-based etch stop layer and expose the surface of the source/drain contact region, by exposing the semiconductor substrate to the plasma comprises a single, continuous etch step to remove the metal-based etch stop layer and expose the surface of the source/drain contact region.

### Claim 15 (depends on 11)

The method of claim 11, further comprising depositing, after exposing the surface of the source/drain contact region, a metal to physically contact the source/drain contact region.

### Claim 16

A method, comprising:
positioning a semiconductor substrate in a plasma process chamber of a plasma process tool, the semiconductor substrate comprising:
a nitride etch stop layer covering a surface of a gate electrode; and
a metal-based etch stop layer covering a surface of a source/drain contact region;
selectively etching the metal-based etch stop layer, to remove the metal-based etch stop layer and expose the surface of the source/drain contact region, by exposing the semiconductor substrate to a plasma formed in a gas comprising chlorine and fluorocarbon, the plasma forming a passivation layer on a surface of the nitride etch stop layer, inhibiting etching of the nitride etch stop layer during exposure of the semiconductor substrate to the plasma such that the surface of the gate electrode remains covered by at least a portion of the nitride etch stop layer following removal of the metal-based etch stop layer.

### Claim 17 (depends on 16)

The method of claim 16, wherein selectively etching the metal-based etch stop layer, to remove the metal-based etch stop layer and expose the surface of the source/drain contact region, by exposing the semiconductor substrate to the plasma formed in the gas comprising chlorine and fluorocarbon, comprises cyclically executing, until the surface of the source/drain contact region is exposed:
forming a passivation layer on the surface of the nitride etch stop layer; and
etching a portion of the metal-based etch stop layer, the passivation layer inhibiting etching of the nitride etch stop layer.

### Claim 18 (depends on 16)

The method of claim 16, wherein the plasma process tool is a capacitively-coupled plasma tool.

### Claim 19 (depends on 16)

The method of claim 16, wherein:
the nitride etch stop layer comprises silicon nitride; and
the metal-based etch stop layer comprises titanium oxide.

### Claim 20 (depends on 1)

The method of claim 1, wherein:
the plasma etching process comprises a reactive ion etching plasma etching process;
the plasma is generated from gases that comprise fluorocarbon, chlorine, and methane, the chlorine being provided at a greater percentage than the fluorocarbon;
the plasma etching process is performed at:
a pressure in a range of 10 mTorr to 20 mTorr;
a low frequency power in a range of 50 W to 200 W; and
a temperature of 20° C. to 80° C.