# US 12,191,201 B2 · Semiconductor device and method for manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,201 B2 - Document ID: US12191201B2 - Status: Granted - Kind: B2 - Application number: 17/755,080 - Filed: 2020-03-16 - Published: 2022-09-15 - Granted: 2025-01-07 - Earliest claimed: 2020-03-16 - Assignees: Mitsubishi Electric Corporation - Applicants: Mitsubishi Electric Corporation - Inventors: Masahiro Totsuka - Web page: https://patentgrep.com/patent/US12191201B2 ## CPC - H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - C23C 16/0272: {Deposition of sub-layers, e.g. to promote the adhesion of the main coating} - C23C 16/045: {Coating cavities or hollow spaces, e.g. interior of tubes; Infiltration of porous substrates} - C23C 16/06: characterised by the deposition of metallic material - C23C 16/45525: {Atomic layer deposition [ALD]} - C23C 16/45529: {specially adapted for making a layer stack of alternating different compositions or gradient compositions} - C23C 16/46: characterised by the method used for heating the substrate (C23C16/48, C23C16/50 take precedence) - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/0261: {characterised by the filling method or the material of the conductive fill} - H10W 20/045: {for deposition from the gaseous phase, e.g. for chemical vapour deposition [CVD]} - H10W 20/425: {Barrier, adhesion or liner layers} - H10W 70/095: {of vias therein} - H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04) ## Abstract An adhesive layer (18) in which the same number of first and second layers (14,16) having conductivity are alternately laminated in order on a semiconductor substrate (10). A metal layer (24) is formed on the adhesive layer (18). The first layer (14) is composed of a material containing an element composing the semiconductor substrate (10). The second layer (16) has higher adhesion to the metal layer (24) than the first layer (14). The adhesive layer (18) has four or more layers including the first and second layers (14,16). Among the first layers (14) and the second layers (16) constituting the adhesive layer (18), excluding the second layer (16) contacting the metal layer (24), the first layer (14) contacting the semiconductor substrate (10) has the largest film thickness, and excluding the first layer (14) contacting the semiconductor substrate (10), the second layer (16) contacting the metal layer (24) has the largest film thickness. ## Claims ### Claim 1 A semiconductor device comprising: a semiconductor substrate including a first surface and a second surface that oppose each other; an adhesive layer in which the same number of first and second layers having conductivity are alternately laminated in order on the first surface; and a metal layer formed on the adhesive layer, wherein the first layer is composed of a material containing an element composing the semiconductor substrate, the second layer has higher adhesion to the metal layer than that of the first layer, the adhesive layer has four or more layers including the first and second layers, among the first layers and the second layers constituting the adhesive layer, excluding the second layer that contacts the metal layer, the first layer that contacts the semiconductor substrate has the largest film thickness, and among the first layers and the second layers, excluding the first layer that contacts the semiconductor substrate, the second layer that contacts the metal layer has the largest film thickness. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein both the first layer that contacts the semiconductor substrate and the second layer that contacts the metal layer have a film thickness of 10 nm or more. ### Claim 3 (depends on 2) The semiconductor device according to claim 2, wherein the semiconductor substrate has a via hole provided therethrough from the first surface to the second surface, an electrode is provided on the second surface and covers the via hole, and the adhesive layer is formed on a surface, which faces the via hole, of the electrode, a side surface of the via hole, and the first surface. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the semiconductor substrate has a via hole provided therethrough from the first surface to the second surface, an electrode is provided on the second surface and covers the via hole, and the adhesive layer is formed on a surface, which faces the via hole, of the electrode, a side surface of the via hole, and the first surface. ### Claim 5 A method for manufacturing a semiconductor device comprising: a first step of forming the same number of first and second layers having conductivity alternately in order on a semiconductor substrate; and a second step of forming a metal layer on the second layer finally formed in the first step, wherein the first layer is composed of a material containing an element composing the semiconductor substrate, the second layer has higher adhesion to the metal layer than that of the first layer, in the first step, four or more layers including the first and second layers are consecutively formed using an ALD method in the same chamber, among the first layers and the second layers formed in the first step, excluding the second layer that contacts the metal layer, the first layer that contacts the semiconductor substrate has the largest film thickness, and among the first layers and the second layers, excluding the first layer that contacts the semiconductor substrate, the second layer that contacts the metal layer has the largest film thickness. ### Claim 6 (depends on 5) The method for manufacturing a semiconductor device according to claim 5, further comprising, between the first step and the second step, a step of performing heat treatment at a higher temperature than an upper-limit film formation temperature when forming the first and second layers in the first step.