# US 12,191,194 B2 · Method for fabricating semiconductor device and reworking process > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,194 B2 - Document ID: US12191194B2 - Status: Granted - Kind: B2 - Application number: 17/709,569 - Filed: 2022-03-31 - Published: 2023-10-05 - Granted: 2025-01-07 - Earliest claimed: 2022-03-31 - Assignees: Nanya Technology Corporation - Applicants: Nanya Technology Corporation - Inventors: Wei-Chen Pan - Web page: https://patentgrep.com/patent/US12191194B2 ## CPC - H10P 50/73: {using masks for insulating materials} - H10W 20/085: {involving intermediate temporary filling with material} - H10P 70/23: {during, before or after processing of insulating materials} - H10P 70/234: {the processing being the formation of vias or contact holes} - H10P 76/4085: {characterised by the processes involved to create the masks} - H10P 76/405: {characterised by their composition, e.g. multilayer masks} - H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers} - H10W 20/42: Vias, e.g. via plugs - H10W 20/4421: {the principal metal being copper} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present application discloses a method for fabricating a semiconductor device including providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening. ## Claims ### Claim 1 A method for fabricating a semiconductor device, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer and the failed hard mask layer; forming an underfill layer to fill the via opening; forming a top hard mask layer on the underfill layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening. ### Claim 2 (depends on 1) The method for fabricating the semiconductor device of claim 1, wherein the underfill layer and the failed hard mask layer comprise different materials. ### Claim 3 (depends on 2) The method for fabricating the semiconductor device of claim 2, wherein a thickness of the failed hard mask layer and a thickness of the underfill layer are different. ### Claim 4 (depends on 3) The method for fabricating the semiconductor device of claim 3, wherein the thickness of the failed hard mask layer is between about 30 nm and about 50 nm. ### Claim 5 (depends on 4) The method for fabricating the semiconductor device of claim 4, wherein the thickness of the underfill layer is between about 180 nm and about 220 nm. ### Claim 6 (depends on 5) The method for fabricating the semiconductor device of claim 5, wherein the dielectric layer comprises a low-k material. ### Claim 7 (depends on 6) The method for fabricating the semiconductor device of claim 6, wherein the top hard mask layer comprises boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride. ### Claim 8 (depends on 7) The method for fabricating the semiconductor device of claim 7, wherein the underfill layer comprises a carbon film. ### Claim 9 (depends on 8) The method for fabricating the semiconductor device of claim 8, wherein the via and the trench comprise copper. ### Claim 10 (depends on 9) The method for fabricating the semiconductor device of claim 9, further comprising forming an etch stop layer between the substrate and the dielectric layer. ### Claim 11 A method for fabricating a semiconductor device, comprising: providing a substrate; forming a dielectric layer on the substrate; forming a via opening in the dielectric layer using a first mask layer as a mask; forming a failed hard mask layer to fill the via opening; forming a second mask layer on the failed hard mask layer; removing the second mask layer; performing a reapplying process to turn the failed hard mask layer into a bottom filling layer; forming a top hard mask layer on the bottom filling layer; forming a third mask layer on the top hard mask layer; patterning the top hard mask layer using the third mask layer as a mask; forming a trench opening in the dielectric layer using the top hard mask layer as a mask; and forming a via in the via opening and forming a trench in the trench opening. ### Claim 12 (depends on 11) The method for fabricating the semiconductor device of claim 11, wherein the bottom filling layer and the failed hard mask layer comprise the same material. ### Claim 13 (depends on 12) The method for fabricating the semiconductor device of claim 12, wherein a thickness of the failed hard mask layer and a thickness of the bottom filling layer are different. ### Claim 14 (depends on 13) The method for fabricating the semiconductor device of claim 13, wherein the thickness of the failed hard mask layer is between about 30 nm and about 50 nm. ### Claim 15 (depends on 14) The method for fabricating the semiconductor device of claim 14, wherein the thickness of the bottom filling layer is between about 180 nm and about 220 nm. ### Claim 16 (depends on 15) The method for fabricating the semiconductor device of claim 15, wherein the dielectric layer comprises a low-k material. ### Claim 17 (depends on 16) The method for fabricating the semiconductor device of claim 16, wherein the top hard mask layer comprises boron nitride, silicon boron nitride, phosphorus boron nitride, or boron carbon silicon nitride. ### Claim 18 (depends on 17) The method for fabricating the semiconductor device of claim 17, further comprising forming an etch stop layer between the substrate and the dielectric layer. ### Claim 19 (depends on 18) The method for fabricating the semiconductor device of claim 18, wherein the etch stop layer comprises silicon carbonitride or silicon oxycarbide. ### Claim 20 (depends on 19) The method for fabricating the semiconductor device of claim 19, wherein the via and the trench comprise copper.