# US 12,191,191 B2 · Semiconductor structure and manufacturing method thereof

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- Number: US 12,191,191 B2
- Document ID: US12191191B2
- Status: Granted
- Kind: B2
- Application number: 17/249,106
- Filed: 2021-02-19
- Published: 2021-07-01
- Granted: 2025-01-07
- Earliest claimed: 2015-12-31
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Min-Ying Tsai; Yeur-Luen Tu
- Web page: https://patentgrep.com/patent/US12191191B2

## CPC

- H10P 90/1914: {using bonding}
- H10F 39/026: {Wafer-level processing}
- H10F 39/18: Complementary metal-oxide-semiconductor [CMOS] image sensors; Photodiode array image sensors
- H10P 50/642: {Chemical etching}
- H10P 50/644: {Anisotropic liquid etching (H10P50/61 takes precedence)}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 72/00: Interconnections or connectors in packages
- H10W 90/00: Package configurations
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/3218: {Phosphides}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10W 72/0198: {batch processes}
- H10W 90/792: {between multiple chips}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure provides a semiconductor structure, including a first semiconductor device having a first surface and a second surface, the second surface being opposite to the first surface, a semiconductor substrate over the first surface of the first semiconductor device, and a III-V etch stop layer in contact with the second surface of the first semiconductor device. The present disclosure also provides a manufacturing method of a semiconductor structure, including providing a temporary substrate having a first surface, forming a III-V etch stop layer over the first surface, forming a first semiconductor device over the etch stop layer, and removing the temporary substrate by an etching operation and exposing a surface of the III-V etch stop layer.

## Claims

### Claim 1

A manufacturing method of a semiconductor structure, comprising:
providing a first substrate having a first surface of silicon;
forming a III-V etch stop layer on the first surface, wherein the III-V etch stop layer is GaP;
providing a device layer on the III-V etch stop layer, wherein the device layer is silicon;
forming a first semiconductor device in the device layer and over the III-V etch stop layer; and
removing the first substrate by a selective etching operation and exposing a surface of the III-V etch stop layer, wherein the selective etching operation includes introducing an etchant selective to a material of the first substrate and stopping at a surface the III-V etch stop layer.

### Claim 2 (depends on 1)

The manufacturing method of claim 1, further comprising bonding the first semiconductor device with a carrier substrate before removing the first substrate.

### Claim 3 (depends on 1)

The manufacturing method of claim 1, wherein the removing the first substrate comprises performing an etch with tetramethylammonium hydroxide.

### Claim 4 (depends on 1)

The manufacturing method of claim 1, wherein the removing the first substrate comprises performing an etch including each of a hydrofluoric acid/nitric acid/acetic acid (HNA) etch and a Tetramethylammonium hydroxide (TMAH) etch, or combinations thereof.

### Claim 5 (depends on 1)

The manufacturing method of claim 1, wherein the forming the III-V etch stop layer comprises performing chemical vapor deposition operation to form an undoped GaP layer.

### Claim 6 (depends on 5)

The manufacturing method of claim 5, wherein the performing the chemical vapor deposition operation comprises forming gallium phosphide epitaxy layer below about 40 nm.

### Claim 7 (depends on 1)

The manufacturing method of claim 1, further comprising removing the III-V etch stop layer after removing the first substrate, wherein the removing includes at least one of Br2 dissolved in methanol or I2 dissolved in methanol.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
epitaxially growing the device layer over the III-V etch stop layer;
forming a transistor on the device layer; and
forming an interconnect conductive trace pattern over the transistor prior to removing the first substrate.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
bonding a second substrate to the interconnect conductive trace pattern prior to removing the first substrate.

### Claim 10 (depends on 9)

The method of claim 9, wherein the second substrate includes a second device layer, a second semiconductor device, and a second interconnect conductive trace pattern, wherein the bonding the second substrate includes interfacing the second interconnect conductive trace pattern with the interconnect conductive trace pattern of the first substrate.

### Claim 11 (depends on 1)

The method of claim 1, wherein the selective etching operation includes:
performing a first wet etch of HF:HNO3:CH3COOH (HNA); and
after the first wet etch, performing a second wet etch of Tetramethylammonium hydroxide (TMAH).

### Claim 12

A method of fabricating a semiconductor device comprising:
providing a first substrate having a surface of a first material;
forming a III-V etch stop layer of a second material on the surface of the first substrate, wherein a lattice mismatch between the first material and the second material is less than about 0.36%;
forming a first device layer over the III-V etch stop layer, wherein the first device layer includes a transistor and a top surface of the first device layer includes a conductive trace pattern within a dielectric layer;
providing a second substrate having a second device layer providing a top surface of another conductive trace pattern within another dielectric layer;
bonding the first substrate and the second substrate by mating the conductive trace pattern and the top surface of the another conductive trace pattern; and
after bonding the first substrate and the second substrate, selectively removing the first substrate and stopping at the III-V etch stop layer, wherein a total thickness variation of the III-V etch stop layer after the selectively removing the first substrate is less than about 1 nanometer (nm).

### Claim 13 (depends on 12)

The method of claim 12, wherein the first material is silicon.

### Claim 14 (depends on 12)

The method of claim 12, wherein the forming the III-V etch stop layer and the forming the first device layer include epitaxial growth processes, wherein the forming the III-V etch stop layer forms the first material of GaP.

### Claim 15 (depends on 12)

The method of claim 12, wherein the selectively removing the first substrate includes:
performing a thinning process of the first substrate to form a thinned first substrate; and
after the thinning process, performing a wet etch of the thinned first substrate, wherein the wet etch includes at least one HF:HNO3:CH3COOH (HNA) or Tetramethylammonium hydroxide (TMAH), and wherein the wet etch removes the thinned first substrate.

### Claim 16 (depends on 15)

The method of claim 15, wherein the wet etch includes a first step of wet etching by HNA followed by a second step of wet etching by TMAH.

### Claim 17

A method of fabricating a semiconductor device comprising:
providing a first substrate comprising silicon and p-type dopant;
depositing a undoped GaP material over the first substrate to form a III-V etch stop layer;
growing a first device layer on the III-V etch stop layer;
forming a transistor, a dielectric layer, and a conductive trace pattern over the first device layer;
providing a second substrate having a bonding surface of another conductive trace pattern within another dielectric layer;
bonding the conductive trace pattern and the dielectric layer to the bonding surface of the second substrate;
after bonding the first substrate and the second substrate, grinding the first substrate to remove a first portion of the first substrate; and
after the grinding, performing a wet etching operation to remove a remaining portion of the first substrate and exposing the III-V etch stop layer.

### Claim 18 (depends on 17)

The method of claim 17, wherein the wet etching operation includes HF:HNO3:CH3COOH (HNA) and Tetramethylammonium hydroxide (TMAH).

### Claim 19 (depends on 17)

The method of claim 17, wherein the performing the wet etching operation includes:
performing a first wet etch of HF:HNO3:CH3COOH (HNA);
performing a polishing process after the first wet etch; and
after the polishing process, performing a second wet etch of Tetramethylammonium hydroxide (TMAH).

### Claim 20 (depends on 17)

The method of claim 17, wherein the first device layer includes a silicon device layer and wherein the second substrate includes a second device layer including III-V material, the second substrate including a transistor on the second device layer and under an upper surface of the another conductive trace pattern.