# US 12,191,182 B2 · Semiconductor device

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- Number: US 12,191,182 B2
- Document ID: US12191182B2
- Status: Granted
- Kind: B2
- Application number: 17/987,867
- Filed: 2022-11-16
- Published: 2023-03-09
- Granted: 2025-01-07
- Earliest claimed: 2020-06-05
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Nuo Wei Luo; Huabiao Wu
- Web page: https://patentgrep.com/patent/US12191182B2

## CPC

- H10P 72/57: {Mask-wafer alignment}
- H10P 76/2041: {Photolithographic processes}
- G03F 7/70633: {Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching}
- G03F 9/7084: {Position of mark on substrate, i.e. position in (x, y, z) of mark, e.g. buried or resist covered mark, mark on rearside, at the substrate edge, in the circuit area, latent image mark, marks in plural levels}
- H10P 76/00: Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 46/101: {characterised by the type of information, e.g. logos or symbols}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided is a semiconductor device includes a substrate, an isolation structure, an alignment mark, and a dielectric layer. The substrate includes a first region and a second region. The isolation structure is disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate. The alignment mark is disposed in the substrate in the second region. The alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure. The dielectric layer is buried in the substrate in the second region and overlapping the alignment mark.

## Claims

### Claim 1

A semiconductor device, comprising:
a substrate including a first region and a second region;
an isolation structure disposed in the substrate in the first region, wherein the isolation structure extends from a first surface of the substrate toward a second surface of the substrate;
an alignment mark in the substrate in the second region, wherein the alignment mark extends from the first surface of the substrate toward the second surface of the substrate and at the same level as the isolation structure;
another isolation structure corresponds to the isolation structure disposed in the substrate in the first region, wherein the another isolation structure extends from the second surface of the substrate toward the first surface of the substrate and aligned to the isolation structure;
a dielectric region buried in the substrate in the second region and overlapping the alignment mark, wherein heteroatoms are ion implanted and annealed to form the dielectric region having a refractive index (n value) less than 1.5 and coplanar with a top surface of the another isolation structure; and
wherein a thickness of a portion of the substrate from the top surface of the another isolation structure to a top surface of the isolation structure is between 4 μm to 20 μm or more and a thickness of a portion of the substrate from a top surface of the alignment mark towards the second surface of the substrate is less than 4 um and greater than 0 um.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein both the first region and the second region are in a chip region.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric region comprises silicon oxide, silicon nitride, or a combination thereof.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric region extends from the second surface of the substrate toward the first surface of the substrate.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein a bottom surface of the dielectric region is in contact with the alignment mark.

### Claim 6 (depends on 4)

The semiconductor device of claim 4, wherein a bottom surface of the dielectric region is separated from the alignment mark by the portion of the dielectric region.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the thickness of the portion of the substrate is less than a distance between a bottom of the isolation structure and the second surface of the substrate.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric region overlaps with the alignment mark the dielectric layer in a vertical direction.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the alignment mark and the isolation structure have a same level.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein the alignment mark and the isolation structure have a same depth.