# US 12,191,163 B2 · Packaged semiconductor devices and methods of packaging semiconductor devices

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- Number: US 12,191,163 B2
- Document ID: US12191163B2
- Status: Granted
- Kind: B2
- Application number: 18/079,504
- Filed: 2022-12-12
- Published: 2023-04-06
- Granted: 2025-01-07
- Earliest claimed: 2015-04-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Hsien-Wei Chen
- Web page: https://patentgrep.com/patent/US12191163B2

## CPC

- H10W 74/01: Manufacture or treatment
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 90/00: Package configurations
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 70/635: {Through-vias}
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/9413: {on encapsulations}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/014: {using batch processing}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die and a first interconnect structure coupled to the integrated circuit die. Through-vias are also coupled to the first interconnect structure. A molding material is disposed around the integrated circuit die and the through-vias over the first interconnect structure. The molding material has a pit disposed therein. A recovery material is disposed within the pit in the molding material. A second interconnect structure is disposed over the molding material, the recovery material, the integrated circuit die, and the through-vias.

## Claims

### Claim 1

A packaged semiconductor device comprising:
an integrated circuit die;
a first interconnect structure coupled to the integrated circuit die;
a plurality of through-vias coupled to the first interconnect structure, the plurality of through-vias disposed in a through-via region surrounding the integrated circuit die;
a molding material disposed over the first interconnect structure and disposed around the integrated circuit die and the plurality of through-vias, the molding material comprising a first indent in a first upper surface thereof;
a recovery material disposed over the molding material and physically contacting the molding material at a location that is within the first indent and that is lower than the first upper surface of the molding material, the recovery material being a different material than the molding material, and the recovering material being an insulating material; and
a second interconnect structure disposed on the recovery material.

### Claim 2 (depends on 1)

The packaged semiconductor device of claim 1, further comprising:
a second indent in a second upper surface of the recovery material corresponding to a location of the first indent, the recovering material being disposed between a bottom of the second indent and the first indent in a cross-sectional view, a portion of the second interconnect structure extending into the second indent.

### Claim 3 (depends on 2)

The packaged semiconductor device of claim 2, wherein the second indent extends below the first upper surface of the molding material, wherein a portion of the second interconnect structure extends into the molding material.

### Claim 4 (depends on 1)

The packaged semiconductor device of claim 1, wherein the recovery material is a second recovery material, wherein a first recovery material is disposed in the first indent, interposed between the second recovery material and the molding material, the first recovery material having a second indent in an upper surface thereof, the second indent being smaller than the first indent.

### Claim 5 (depends on 1)

The packaged semiconductor device of claim 1, wherein the first indent has a first depth between 3 μm and 50 μm and a first width between 6.5 μm and 200 μm.

### Claim 6 (depends on 1)

The packaged semiconductor device of claim 1, wherein the recovery material has a same lateral extent as the molding material.

### Claim 7 (depends on 1)

The packaged semiconductor device of claim 1, further comprising a through molding via (TMV) extending through the molding material, the first indent disposed between the TMV and the integrated circuit die.

### Claim 8

A device comprising:
a conductive column disposed on a first redistribution structure;
a die disposed on the first redistribution structure, an active side of the die being face up away from the first redistribution structure;
a molding material laterally surrounding the die and the conductive column, the conductive column extending continuously from an upper surface of the molding material to a bottom surface of the molding material, a first indentation disposed in the upper surface of the molding material adjacent the active side of the die, the first indentation being disposed between the die and the conductive column, and the molding material being disposed between first indentation and the conductive column;
a recovery material disposed in the first indentation, the recovery material comprising a material different from the molding material, the recovery material extending laterally beyond an edge of the first indentation; and
a second redistribution structure disposed on the recovery material.

### Claim 9 (depends on 8)

The device of claim 8, wherein the recovery material comprises a second indentation disposed in the recovery material, the second indentation aligned to the first indentation, wherein a portion of the second redistribution structure extends into the second indentation.

### Claim 10 (depends on 9)

The device of claim 9, wherein the portion of the second redistribution structure extending into the second indentation is at least partially laterally surrounded by the molding material.

### Claim 11 (depends on 8)

The device of claim 8, wherein the first indentation has a first depth between 3 μm and 50 μm and a first width between 6.5 μm and 200 μm.

### Claim 12 (depends on 8)

The device of claim 8, wherein the recovery material extends laterally to an edge of the second redistribution structure.

### Claim 13 (depends on 8)

The device of claim 8, wherein the second redistribution structure includes a first insulating layer, the first insulating layer interfacing with the recovery material, wherein the first insulating layer and the recovery material are comprised of different material compositions.

### Claim 14 (depends on 8)

The device of claim 8, wherein the recovery material extends over and contacts and upper surface of the conductive column.

### Claim 15

A structure comprising:
an encapsulant laterally surrounding an embedded die, wherein the encapsulant is a molding material;
a first indentation in the encapsulant, the first indentation having a first depth;
a first recovery material lining the first indentation, the first recovery material further extending over the encapsulant, the first recovery material being an insulating material, and the first recovery material physically contacting the encapsulant at a lowest point of the first indentation in a cross-sectional view; and
a redistribution structure disposed over the first recovery material and the embedded die wherein the redistribution structure is electrically connected to the embedded die.

### Claim 16 (depends on 15)

The structure of claim 15 further comprising a second indentation in the first recovery material.

### Claim 17 (depends on 16)

The structure of claim 16, wherein the second indentation has a second depth that is less than the first depth.

### Claim 18 (depends on 16)

The structure of claim 16, further comprising a second recovery material in the second indentation.

### Claim 19 (depends on 15)

The structure of claim 15, wherein the redistribution structure extends below a top surface of the encapsulant in the first indentation.

### Claim 20 (depends on 15)

The structure of claim 15, wherein the first recovery material is laterally coterminous with the encapsulant.