# US 12,191,162 B2 · Semiconductor device assembly with pillar array

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- Number: US 12,191,162 B2
- Document ID: US12191162B2
- Status: Granted
- Kind: B2
- Application number: 17/189,006
- Filed: 2021-03-01
- Published: 2021-06-17
- Granted: 2025-01-07
- Earliest claimed: 2017-12-04
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Owen R. Fay; Akshay N. Singh; Kyle K. Kirby
- Web page: https://patentgrep.com/patent/US12191162B2

## CPC

- H10W 70/095: {of vias therein}
- H10P 74/23: {characterised by multiple measurements, corrections, marking or sorting processes}
- H10P 74/273: {Interconnections for measuring or testing, e.g. probe pads}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/635: {Through-vias}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/685: comprising multiple insulating layers
- H10W 72/072: {of bump connectors}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/284: {characterised by structural arrangements for measuring or testing}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

## Claims

### Claim 1

A semiconductor device assembly comprising:
a first substrate having a top surface and a bottom surface opposite the top surface;
a second substrate having a top surface and a bottom surface opposite the top surface, the second substrate being disposed over the first substrate;
an interconnect between the first substate and the second substrate that electrically connects the first substrate with the second substrate;
an array of pillars of conductive material that extend outwardly from the bottom surface of the first substrate, the array of pillars being positioned adjacent to a first lateral side of the first substrate and wherein a portion of the array of pillars is positioned within the first substrate;
at least one pad on the top surface of the substrate, the at least one pad being positioned adjacent to the first lateral side of the first substrate;
a plurality of interconnections within the first substrate and coupled at an upper portion of the array of pillars facing the top surface of the substrate, the plurality of interconnections electrically connecting the array of pillars with the interconnect between the first substrate and the second substrate, the at least one pad with the interconnect between the first substrate and the second substrate, and the at least one pad with the array of pillars; and
wherein the first substrate has a first area and the second substrate has a second area that is smaller than the first area and wherein the at least one pad and the array of pillars are offset from the second substrate.

### Claim 2 (depends on 1)

The semiconductor device assembly of claim 1, wherein the array of pillars is positioned opposite of the at least one pad.

### Claim 3 (depends on 2)

The semiconductor device assembly of claim 2, comprising a third substrate disposed over the second substrate, the third substrate is electrically connected to the first substrate via the second substrate.

### Claim 4 (depends on 3)

The semiconductor device assembly of claim 3, wherein the second substrate and third substrate comprise a memory stack.

### Claim 5 (depends on 3)

The semiconductor device assembly of claim 3, comprising a fourth substrate disposed over the third substrate, the fourth substrate is electrically connected to the first substrate via the second substrate and third substrate.

### Claim 6 (depends on 5)

The semiconductor device assembly of claim 5, wherein the second substrate, the third substrate, and the fourth substrate comprise a memory stack.

### Claim 7 (depends on 2)

The semiconductor device assembly of claim 2, wherein the array of pillars of conductive material has a third area, wherein the third area is less than half of the first area.

### Claim 8 (depends on 7)

The semiconductor device assembly of claim 7, wherein the third area is thirteen millimeters by six millimeters.

### Claim 9 (depends on 2)

The semiconductor device assembly of claim 2, further comprising a pad on an end of each individual pillar of the array of pillars.

### Claim 10

A semiconductor device assembly comprising:
a substrate having a top surface, a bottom surface opposite the top surface, a first lateral side, a second lateral side opposite the first side, a first end, and a second end opposite the first end;
a memory stack disposed over the top surface of the substrate;
at least one interconnect between the memory stack and the top surface of the substrate;
a pillar array that extends outwardly from the bottom surface of the substrate a portion of the pillar array being positioned within the substrate, each pillar of the pillar array being comprised of a conductive material, wherein the pillar array is positioned adjacent the first lateral side of the substrate and is not adjacent the second lateral side, the first end, and the second end; and
a plurality of interconnections within the substrate and coupled at an upper portion of the pillar array facing the top surface of the substrate, the plurality of interconnections electrically connecting the pillar array with the at least one interconnect between the memory stack and the top surface of the substrate.

### Claim 11 (depends on 10)

The semiconductor device assembly of claim 10, comprising a pad connected to an end of each pillar of the pillar array.

### Claim 12 (depends on 10)

The semiconductor device assembly of claim 10, comprising one or more pads on the bottom surface of the substrate, wherein the plurality of interconnections within the substrate electrically connect the one or more pads with the pillar array and with the at least one interconnect between the memory stack and the top surface of the substrate.

### Claim 13 (depends on 12)

The semiconductor device assembly of claim 12, comprising a pad connected to an end of each pillar of the pillar array.

### Claim 14 (depends on 10)

The semiconductor device assembly of claim 10, comprising:
one or more pads located adjacent to the bottom surface of the substrate, wherein a layer of silicon covers the one or more pads and wherein the plurality of interconnections within the substrate electrically connect the one or more pads with the pillar array and with the at least one interconnect between the memory stack and the top surface of the substrate;
wherein the pillar array extends through the layer of silicon; and
an exterior coating on each pillar of the pillar array.

### Claim 15 (depends on 14)

The semiconductor device assembly of claim 14, comprising a pad connected to an end of each pillar of the pillar array.

### Claim 16 (depends on 14)

The semiconductor device assembly of claim 14, wherein the exterior coating comprises tantalum.

### Claim 17 (depends on 10)

The semiconductor device assembly of claim 10, further comprising:
a first pad on the top surface of the substrate, wherein the plurality of interconnections within the substrate electrically connect the first pad with the pillar array and with the at least one interconnect between the memory stack and the top surface of the substrate;
a second pad on the top surface of the substrate, wherein the plurality of interconnections within the substrate electrically connect the second pad with the pillar array and with the at least one interconnect between the memory stack and the top surface of the substrate; and
wherein the memory stack is positioned between the first pad and the second pad.

### Claim 18 (depends on 17)

The semiconductor device assembly of claim 17, comprising a pad connected to an end of each pillar of the pillar array.

### Claim 19 (depends on 10)

The semiconductor device assembly of claim 10, further comprising:
a first pad on the top surface of the substrate, wherein the plurality of interconnections within the substrate electrically connect the first pad with the pillar array and with the at least one interconnect between the memory stack and the top surface of the substrate;
a second pad on the top surface of the substrate, wherein the plurality of interconnections within the substrate electrically connect the second pad with the pillar array and with the at least one interconnect between the memory stack and the top surface of the substrate; and
wherein the first pad and the second pad are adjacent the first lateral side of the substrate opposite the pillar array.

### Claim 20 (depends on 19)

The semiconductor device assembly of claim 19, comprising a pad connected to an end of each pillar of the pillar array.