# US 12,191,158 B2 · Semiconductor device and method

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- Number: US 12,191,158 B2
- Document ID: US12191158B2
- Status: Granted
- Kind: B2
- Application number: 17/513,708
- Filed: 2021-10-28
- Published: 2022-11-17
- Granted: 2025-01-07
- Earliest claimed: 2021-05-12
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Kuan-Wei Huang
- Web page: https://patentgrep.com/patent/US12191158B2

## CPC

- H10P 50/73: {using masks for insulating materials}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P 50/283: {by chemical means}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/098: {by filling between adjacent conductive parts}
- H10W 20/084: {for dual-damascene structures}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for manufacturing a semiconductor device includes depositing a first hard mask layer and a first dielectric layer over a substrate, forming a patterned layer over the first dielectric layer, forming a second hard mask layer over the patterned layer, patterning the second hard mask layer to remove first horizontal portions of the second hard mask layer and leave second portions of the second hard mask layer along sidewalls of the patterned layer, etching a trench in the first dielectric layer using the second portions of the second hard mask layer and the patterned layer as an etching mask, depositing a first gap-filling material in the trench and patterning the first hard mask layer using the first gap-filling material, the patterned layer, and the second portions of the second hard mask layer as a mask.

## Claims

### Claim 1

A method for manufacturing a semiconductor device comprising:
depositing a first hard mask layer and a first dielectric layer over a substrate;
forming a patterned layer over the first dielectric layer;
forming a second hard mask layer over the patterned layer;
patterning the second hard mask layer to remove first horizontal portions of the second hard mask layer and leave second portions of the second hard mask layer along sidewalls of the patterned layer;
etching the first dielectric layer using the second portions of the second hard mask layer and the patterned layer as an etching mask creating by that a trench that extends through the patterned layer and the first dielectric layer;
depositing a first gap-filling material in the trench; and
patterning the first hard mask layer using the first gap-filling material, the patterned layer, and the second portions of the second hard mask layer as a mask.

### Claim 2 (depends on 1)

The method of claim 1, wherein patterning the second hard mask layer and etching the trench in the first dielectric layer comprises a continuous etching process.

### Claim 3 (depends on 2)

The method of claim 2, wherein the continuous etching process comprises an etchant that includes carbon tetrafluoride (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), or hexafluorobutadiene (C4F6).

### Claim 4 (depends on 2)

The method of claim 2, wherein the continuous etching process comprises flowing a carrier gas that includes nitrogen, helium, or argon.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first hard mask layer comprises tungsten dicarbide, and, wherein the second hard mask layer comprises titanium oxide.

### Claim 6 (depends on 1)

The method of claim 1, wherein the etch selectivity ratio between the first hard mask layer and the first gap-filling material is higher than 6.

### Claim 7 (depends on 1)

The method of claim 1, wherein depositing the first gap-filling material in the trench comprises:
forming a mask layer in the trench and over the patterned layer and the second portions of the second hard mask layer;
forming an opening in the mask layer, and removing, during this step, a portion of the mask layer that filled the trench;
depositing the first gap-filling material in the opening, including the trench; and
reducing the height of the first gap-filling material.

### Claim 8 (depends on 7)

The method of claim 7, wherein depositing the first gap-filling material comprises forming an oxide using an atomic layer deposition (ALD) process.

### Claim 9

A method for manufacturing a semiconductor device comprising:
depositing a first dielectric layer over a first hard mask layer;
forming a patterned layer over the first dielectric layer;
forming spacers along sidewalls of the patterned layer, a first trench being between sidewalls of adjacent ones of the spacers;
creating an extended first trench by extending the first trench through the first dielectric layer;
depositing a mask layer in the extended first trench, and over the spacers and the patterned layer;
forming an opening in the mask layer, the opening passing through the extended first trench;
filling the extended first trench with a first gap-filling material; and
patterning the first hard mask layer using the spacers, the patterned layer and the first gap-filling material as a mask.

### Claim 10 (depends on 9)

The method of claim 9, wherein forming the spacers comprises:
forming a second hard mask layer over the patterned layer and the first dielectric layer;
etching first portions of the second hard mask layer over the patterned layer; and
etching second portions of the second hard mask layer over the first dielectric layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein forming the spacers and extending the first trench comprises a continuous etching process using an etchant that includes CF4, CHF3, CH2F2, or C4F6.

### Claim 12 (depends on 9)

The method of claim 9, wherein a height of the patterned layer is in a range from 150 Å to 500 Å.

### Claim 13 (depends on 9)

The method of claim 9, wherein extending the first trench through the first dielectric layer comprises exposing a top surface of the first hard mask layer.

### Claim 14 (depends on 9)

The method of claim 9, wherein filling the extended first trench with the first gap-filling material comprises filling first gap-filling material in physical contact with a top surface of the first hard mask layer.

### Claim 15 (depends on 9)

The method of claim 9, wherein the first dielectric layer comprises tetetraethyl orthosilicate (TEOS), silicon nitride (SiN), or silicon oxynitride (SiON).

### Claim 16

A method for manufacturing a semiconductor device comprising:
forming a first hard mask layer over a target layer;
forming a first dielectric layer and a patterned layer successively over the first hard mask layer;
forming a first portion of a hard mask on sidewalls of the patterned layer;
patterning the first dielectric layer and forming a trench that extends through the patterned layer and the first dielectric layer;
depositing a first gap-filling material in the trench to form a second portion of the hard mask;
patterning the first hard mask layer using the first portion of the hard mask and the second portion of the hard mask as parts of an etching mask; and
transferring the pattern of the first hard mask layer to the target layer.

### Claim 17 (depends on 16)

The method of claim 16 wherein the first hard mask layer comprises a percentage carbon content that is in a range from 40 percent to 60 percent.

### Claim 18 (depends on 16)

The method of claim 16, wherein the first portion of the hard mask comprises titanium oxide, titanium nitride or titanium silicon oxide.

### Claim 19 (depends on 16)

The method of claim 16, wherein depositing the first gap-filling material in the trench comprises depositing the first gap-filling material in physical contact with the first portion of the hard mask, the first hard mask layer, and the first dielectric layer.

### Claim 20 (depends on 16)

The method of claim 16, wherein depositing the first gap-filling material comprises forming a carbon based material using a spin-coating process.