# US 12,191,157 B2 · Manufacturing method of semiconductor memory device

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- Number: US 12,191,157 B2
- Document ID: US12191157B2
- Status: Granted
- Kind: B2
- Application number: 17/685,611
- Filed: 2022-03-03
- Published: 2023-04-27
- Granted: 2025-01-07
- Earliest claimed: 2021-10-26
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Seung Cheol Lee; Dae Min Kim; Dae Sung Kim; Sang Seob Lee; Hyun Woo Jin
- Web page: https://patentgrep.com/patent/US12191157B2

## CPC

- H10P 50/283: {by chemical means}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10P 70/23: {during, before or after processing of insulating materials}
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/41: of a memory region comprising a cell select transistor, e.g. NAND
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of manufacturing a semiconductor memory device includes alternately stacking sacrificial layers and interlayer insulating layers over a lower structure, forming a slit passing through the sacrificial layers and the interlayer insulating layers, removing the sacrificial layers through the slit through a wet etching process, and removing, through a dry etching process, a byproduct that is produced at ends of the interlayer insulating layers during the wet etching process.

## Claims

### Claim 1

A method of manufacturing a semiconductor memory device, the method comprising:
alternately stacking sacrificial layers and interlayer insulating layers over a lower structure;
forming a slit passing through the sacrificial layers and the interlayer insulating layers;
removing the sacrificial layers through the slit through a wet etching process; and
removing, through a dry etching process, a byproduct that is produced at ends of the interlayer insulating layers during the wet etching process.

### Claim 2 (depends on 1)

The method of claim 1, wherein phosphoric acid is used in the wet etching process.

### Claim 3 (depends on 1)

The method of claim 1, wherein the byproduct includes silicic acid.

### Claim 4 (depends on 3)

The method of claim 3, wherein the silicic acid includes SiOH.

### Claim 5 (depends on 3)

The method of claim 3, wherein the dry etching process includes an operation of forming an HF2− ion.

### Claim 6 (depends on 5)

The method of claim 5, wherein the HF2− ion is formed by injecting water vapor that has a flow rate of 1000 mgm to 3000 mgm, nitrogen trifluoride (NF3) gas that has a flow rate of 10 sccm to 25 sccm, and oxygen (O2) gas that has a flow rate of 100 sccm to 200 sccm into a reaction chamber to which a pressure of 7 Torr to 10 Torr and electric power of 100 W to 350 W are applied.

### Claim 7 (depends on 5)

The method of claim 5, wherein silicon tetrafluoride (SiF4) is produced through a reaction between the silicic acid and the HF2− ion during the dry etching process.

### Claim 8 (depends on 7)

The method of claim 7, further comprising removing the silicon tetrafluoride (SiF4) by using deionized (DI) water.

### Claim 9 (depends on 1)

The method of claim 1, wherein the byproduct with respect to the interlayer insulating layers is selectively removed through the dry etching process.

### Claim 10 (depends on 1)

The method of claim 1, wherein the dry etching process makes an etch selectivity of the byproduct with respect to the interlayer insulating layers greater than or equal to 1.

### Claim 11 (depends on 10)

The method of claim 10, wherein the etch selectivity is 1.2.