# US 12,191,154 B2 · Method for manufacturing semiconductor structure, semiconductor structure, and memory

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- Number: US 12,191,154 B2
- Document ID: US12191154B2
- Status: Granted
- Kind: B2
- Application number: 17/486,707
- Filed: 2021-09-27
- Published: 2023-01-19
- Granted: 2025-01-07
- Earliest claimed: 2021-07-13
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Junbo Pan
- Web page: https://patentgrep.com/patent/US12191154B2

## CPC

- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 50/691: {for Group IV materials or Group III-V materials}
- H10P 76/00: Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
- H10P 76/2041: {Photolithographic processes}
- H10B 12/01: {Manufacture or treatment}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

The present application provides a method for manufacturing a semiconductor structure, a semiconductor structure, and a memory. The method for manufacturing a semiconductor structure includes the following steps: providing a substrate, and forming a stabilizing layer on the substrate; forming a stabilizing structure consisting of a plurality of linear structures and grooves among the linear structures; forming a hard mask layer covering the stabilizing structure; forming a mask pattern connected to a top of the linear structure and an inner wall of the groove on the hard mask layer; and transferring the mask pattern to the substrate.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate, and forming a stabilizing layer on the substrate;
forming a stabilizing structure consisting of a plurality of linear structures and grooves among the linear structures on the stabilizing layer;
forming a hard mask layer covering the stabilizing structure;
forming a mask pattern connected to a top of the linear structures and an inner wall of the grooves on the hard mask layer;
transferring the mask pattern to the substrate; and
removing the mask pattern and the stabilizing structure; and,
wherein forming the mask pattern connected to the top of the linear structures and the inner wall of the grooves on the hard mask layer comprises:
etching the hard mask layer to form a plurality of hard mask layer strips, wherein thehard mask layer strips are arranged at intervals to form the mask pattern; wherein a preset included angle is formed between a length direction of the hard mask layer strips and a length direction of the linear structures.

### Claim 2 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein the forming the stabilizing structure consisting of the plurality of linear structures and the grooves among the linear structures on the stabilizing layer comprises:
forming a photoresist layer on the stabilizing layer, wherein the photoresist layer is formed with a target pattern;
etching the stabilizing layer according to the target pattern; and
removing the photoresist layer after the etching to form the stabilizing structure.

### Claim 3 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein
in a length direction of the linear structures, the linear structures each have a rectangular cross section.

### Claim 4 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein
in a length direction of the linear structures, the grooves each have a rectangular cross section.

### Claim 5 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein
in a direction perpendicular to a length direction of the linear structures, the linear structures each have a width greater than the grooves.

### Claim 6 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein prior to the etching the hard mask layer, the method further comprises:
forming a photoresist layer on the hard mask layer, wherein the photoresist layer constitutes the mask pattern.

### Claim 7 (depends on 6)

The method for manufacturing the semiconductor structure according to claim 6, wherein
forming the photoresist layer on the hard mask layer comprises forming the photoresist layer on the hard mask layer with a spin coating process.

### Claim 8 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein
the preset included angle between the length direction of the hard mask layer strips formed with an etching process and the length direction of the linear structures is within a range of 30° to 60°.

### Claim 9 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein
in the length direction of the hard mask layer strips, each of the hard mask layer strips is formed to be connected to the top of at least one of the linear structures or the inner wall of at least one of the grooves.

### Claim 10 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein subsequent to the forming the mask pattern on the hard mask layer, the method further comprises:
cleaning the mask pattern.

### Claim 11 (depends on 1)

The method for manufacturing the semiconductor structure according to claim 1, wherein the transferring the mask pattern to the substrate comprises:
transferring the mask pattern to the substrate with a dry etching process.

### Claim 12 (depends on 1)

A semiconductor structure, wherein the semiconductor structure is formed by the method for manufacturing the semiconductor structure according to claim 1.

### Claim 13 (depends on 12)

A memory, comprising the semiconductor structure according to claim 12.