Gate-all-around transistor with reduced source/drain contact resistance

A method comprising:

• forming a gate stack on a multilayer stack, wherein the multilayer stack comprises a plurality of sacrificial layers and a plurality of semiconductor layers, and wherein the plurality of sacrificial layers and the plurality of semiconductor layers are located alternatingly, and a bottom surface of the gate stack contacts a topmost surface of a topmost one of the plurality of semiconductor layers;
• etching a an inter-layer dielectric and a Contact Etch Stop Layer (CESL) to form a contact opening and to reveal a semiconductor region, wherein the semiconductor region is aside of the multilayer stack;
• etching the semiconductor region to extend the contact opening further into the semiconductor region, wherein the semiconductor region has a first top surface higher than a level of the topmost surface, and the etching the semiconductor region is performed until an additional bottom surface of the contact opening is lower than the level of topmost surface;
• depositing a metal layer, wherein the metal layer extends into the contact opening;
• depositing a capping layer over the metal layer;
• and
• performing an annealing process, wherein a bottom portion of the metal layer reacts with the semiconductor region to form a silicide region.

A method comprising:

• forming a gate stack;
• growing a source/drain region on a side of the gate stack through epitaxy;
• depositing a contact etch stop layer (CESL) over the source/drain region;
• depositing an inter-layer dielectric over the CESL;
• etching the inter-layer dielectric and the CESL to form a contact opening;
• etching the source/drain region so that the contact opening extends into the source/drain region;
• depositing a metal layer extending into the contact opening, wherein horizontal portions, vertical portions, and corner portions of the metal layer have a substantially uniform thickness;
• performing an annealing process to react the metal layer with the source/drain region, wherein a source/drain silicide region is formed;
• and
• filling the contact opening to form a source/drain contact plug, wherein the source/drain silicide region extends laterally beyond edges of the source/drain contact plug by distances greater than about 2 nm.