# US 12,191,145 B2 · Semiconductor device and formation method thereof

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- Number: US 12,191,145 B2
- Document ID: US12191145B2
- Status: Granted
- Kind: B2
- Application number: 17/834,596
- Filed: 2022-06-07
- Published: 2023-12-07
- Granted: 2025-01-07
- Earliest claimed: 2022-06-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University
- Inventors: Chia-Che Chung; Chia-Jung Tsen; Chee-Wee Liu
- Web page: https://patentgrep.com/patent/US12191145B2

## CPC

- H10P 14/40: of conductive or resistive materials
- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10P 14/6328: {Deposition from the gas or vapour phase}
- H10P 14/668: {the materials being characterised by the deposition precursor materials}
- H10P 14/68: Organic materials, e.g. photoresists
- H10P 14/6939: {characterised by the metal}
- H10P 14/69391: {the material containing aluminium, e.g. Al2O3}
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0261: {characterised by the filling method or the material of the conductive fill}
- H10W 20/0265: {characterised by the sidewall insulation}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of forming a semiconductor device includes forming a semiconductor strip extending above a semiconductor substrate, forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip, recessing a portion of the semiconductor strip, etching the STI regions to form a recess in the STI regions, forming a first thermal conductive layer in the recess, forming a source/drain epitaxy structure on the first thermal conductive layer, and forming a gate stack across the semiconductor strip and extending over the STI regions.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
forming a semiconductor strip extending above a semiconductor substrate;
forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip;
recessing a portion of the semiconductor strip;
etching the STI regions to form a recess in the STI regions;
forming a first thermal conductive layer in the recess, wherein forming the first thermal conductive layer comprises:
depositing a first thermal conductive material filling into the recess in the STI regions;
etching back the first thermal conductive material;
forming a patterned photoresist over the etched back first thermal conductive material; and
etching the first thermal conductive material using the patterned photoresist as a mask;
forming a source/drain epitaxy structure on the first thermal conductive layer; and
forming a gate stack across the semiconductor strip and extending over the STI regions.

### Claim 2 (depends on 1)

Method of claim 1, wherein the first thermal conductive layer is made of BeO, AlN, or chemical vapor deposited diamond.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first thermal conductive layer has a thermal conductivity of greater than 1.4 W/m·K.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
forming a second thermal conductive layer covering the source/drain epitaxy structure.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming a source/drain contact penetrating through the second thermal conductive layer to be in contact with the source/drain epitaxy structure.

### Claim 6 (depends on 4)

The method of claim 4, wherein the second thermal conductive layer includes BeO, AlN, or chemical vapor deposited diamond.

### Claim 7 (depends on 4)

The method of claim 4, wherein the second thermal conductive layer and the first thermal conductive layer collectively surround the source/drain epitaxy structure.

### Claim 8

A method of forming a semiconductor device, comprising:
forming a semiconductor strip extending above a front-side of a semiconductor substrate, wherein the semiconductor substrate has a back-side opposite to the front-side;
forming shallow trench isolation (STI) regions on opposite sides of the semiconductor strip;
recessing a portion of the semiconductor strip;
after recessing the portion of the semiconductor strip, forming a mask layer on the STI regions;
forming a patterned photoresist over the mask layer;
etching the STI regions using the mask layer and the patterned photoresist as an etch mask to form a recess in the STI regions;
forming a dielectric layer on the recessed portion of the semiconductor strip;
forming a source/drain epitaxy structure on the dielectric layer, wherein the source/drain epitaxy structure is in contact with the dielectric layer; and
forming a gate stack across the semiconductor strip and extending over the STI regions.

### Claim 9 (depends on 8)

The method of claim 8, wherein the dielectric layer is in contact with opposite sidewalls of the source/drain epitaxy structure.

### Claim 10 (depends on 8)

The method of claim 8, wherein the dielectric layer has a thermal conductivity greater than a thermal conductivity of silicon oxide.

### Claim 11 (depends on 8)

The method of claim 8, wherein the recessed portion of the semiconductor strip is separated with the source/drain epitaxy structure by the dielectric layer.

### Claim 12 (depends on 8)

The method of claim 8, wherein the dielectric layer has a U-shaped profile when viewed from cross-section.

### Claim 13 (depends on 8)

The method of claim 8, wherein the dielectric layer is in contact with a top surface of the STI regions and a sidewall of the STI regions.

### Claim 14 (depends on 8)

The method of claim 8, wherein forming the dielectric layer is performed using atomic layer deposition, chemical vapor deposition, or physical vapor deposition.

### Claim 15 (depends on 8)

The method of claim 8, further comprising:
forming a back-end-of-line (BEOL) stack on the front-side of the semiconductor substrate, wherein the BEOL stack is electrically connected to the gate stack or the source/drain epitaxy structure; and
forming a through substrate via (TSV) penetrating from the back-side of the semiconductor substrate into the semiconductor substrate, wherein the TSV is electrically connected to the BEOL stack.

### Claim 16

A method of forming a semiconductor device, comprising:
forming a semiconductor strip on a front-side of a semiconductor substrate;
forming shallow trench isolation (STI) regions on the semiconductor substrate;
forming a gate crossing the semiconductor strip;
forming a first thermal conductive layer over the semiconductor strip, wherein the first thermal conductive layer has a thermal conductivity greater than 1.4 W/m·K; and
forming source/drain epitaxy structures on opposite sides of the gate, wherein the first thermal conductive layer laterally surrounds a bottom of the source/drain epitaxy structures;
forming a back-end-of-line (BEOL) stack on a front-side of the semiconductor substrate and being electrically connected to the gate or the source/drain epitaxy structures; and
forming a through-substrate via (TSV) penetrating through a back-side of the semiconductor substrate opposite to the front-side, wherein the TSV has a first edge opposite to a second edge of the source/drain epitaxy structures, and the first edge and the second edge have a lateral distance in a range from 0.1 μm to 100 μm.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first thermal conductive layer has a portion between the semiconductor strip and the source/drain epitaxy structures in a vertical direction.

### Claim 18 (depends on 16)

The method of claim 16, further comprising:
forming a second thermal conductive layer covering a top of the source/drain epitaxy structures.

### Claim 19 (depends on 16)

The method of claim 16, wherein the first thermal conductive layer is BeO, AlN, or chemical vapor deposited diamond.

### Claim 20 (depends on 16)

The method of claim 16, wherein the first thermal conductive layer has a top surface substantially coplanar with a top surface of the STI regions.