# US 12,191,144 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 12,191,144 B2
- Document ID: US12191144B2
- Status: Granted
- Kind: B2
- Application number: 17/876,487
- Filed: 2022-07-28
- Published: 2022-11-24
- Granted: 2025-01-07
- Earliest claimed: 2020-04-01
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.; National Taiwan University; National Taiwan Normal University
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.; National Taiwan University; National Taiwan Normal University
- Inventors: Chun-Yi Chou; Po-Hsien Cheng; Tse-An Chen; Miin-Jang Chen
- Web page: https://patentgrep.com/patent/US12191144B2

## CPC

- H10P 14/6339: {deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD}
- C23C 16/042: {using masks}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/01: Manufacture or treatment
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/01342: {by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/853: {comprising FinFETs}
- H10P 14/61: using masks
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/074: {of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers}
- H10W 20/42: Vias, e.g. via plugs
- H10D 30/792: {comprising applied insulating layers, e.g. stress liners}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/822: comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- C23C: COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL (making metal-coated products by extrusion B21C23/22; covering with metal by connecting pre-existing layers to articles, see the relevant places, e.g. B21D39/00, B23K; metallising of glass C03C; metallising mortars, concrete, artificial stone, ceramics or natural stone C04B41/00; enamelling of, or applying a vitreous layer to, metals C23D; treating metal surfaces or coating of metals by electrolysis or electrophoresis C25D; single-crystal film growth C30B; by metallising textiles D06M11/83; decorating textiles by locally metallising D06Q1/04)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes forming a mask layer above a substrate. The substrate is patterned by using the mask layer as a mask to form a trench in the substrate. An isolation structure is formed in the trench, including feeding first precursors to the substrate. A bias is applied to the substrate after feeding the first precursors. With the bias turned on, second precursors are fed to the substrate. Feeding the first precursors, applying the bias, and feeding the second precursors are repeated.

## Claims

### Claim 1

A method comprising:
forming a mask layer above a substrate;
patterning the substrate by using the mask layer as a mask to form a trench in the substrate; and
forming an isolation structure in the trench, comprising:
feeding first precursors to the substrate;
applying a bias to the substrate for a first duration time after feeding the first precursors;
with the bias turned on, feeding second precursors to the substrate for a second duration time shorter than the first duration time of applying the bias; and
repeating feeding the first precursors, applying the bias, and feeding the second precursors.

### Claim 2 (depends on 1)

The method of claim 1, wherein the bias is a positive bias.

### Claim 3 (depends on 1)

The method of claim 1, wherein the bias is a negative bias.

### Claim 4 (depends on 1)

The method of claim 1, wherein the first precursors are silicon precursors.

### Claim 5 (depends on 1)

The method of claim 1, wherein the second precursors are H2O.

### Claim 6 (depends on 1)

The method of claim 1, wherein a power of the bias is greater than about 0 W and equal to or less than 50 W.

### Claim 7 (depends on 1)

The method of claim 1, wherein the bias is turned off after stopping feeding the second precursors.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
performing a chemical-mechanical polishing process on the isolation structure.

### Claim 9 (depends on 8)

The method of claim 8, further comprising:
recessing the isolation structure such that fins of the substrate protrude above the recessed isolation structure.

### Claim 10 (depends on 1)

The method of claim 1, wherein a deposition rate of the second precursors over the substrate is greater than a deposition rate of the second precursors over the mask layer.

### Claim 11

A method comprising:
forming a mask layer above a substrate;
patterning the substrate by using the mask layer as a mask to form a trench in the substrate; and
forming an isolation structure in the trench by using an atomic layer deposition (ALD) process, the ALD process comprises one or more repetitions of an ALD cycle, the ALD cycle comprising:
applying a bias to the substrate;
during applying the bias to the substrate, feeding first precursors to the substrate such that a deposition rate of the first precursors over the substrate is greater than a deposition rate of the first precursors over the mask layer;
turning off the bias; and
after turning off the bias, feeding second precursors to the substrate.

### Claim 12 (depends on 11)

The method of claim 11, wherein the bias is less than 50 W.

### Claim 13 (depends on 11)

The method of claim 11, wherein the first precursors are H2O.

### Claim 14 (depends on 11)

The method of claim 11, wherein the second precursors are silicon precursors.

### Claim 15 (depends on 11)

The method of claim 11, further comprising:
stopping feeding the first precursors before turning off the bias.

### Claim 16 (depends on 11)

The method of claim 11, wherein the bias is an RF bias.

### Claim 17 (depends on 11)

The method of claim 11, wherein applying the bias to the substrate is performed such that more electrons are accumulated on a surface of the mask layer than on a surface of the substrate.

### Claim 18 (depends on 11)

The method of claim 11, further comprising:
forming terminating species on the substrate and the mask layer before forming the isolation structure, the terminating species comprising-OH.

### Claim 19

A method comprising:
forming a mask layer over a substrate;
etching the substrate by using the mask layer as an etch mask to form semiconductor fins; and
performing a deposition process to deposit a dielectric material over the semiconductor fins, the deposition process comprising one or more repetitions of a deposition cycle, the deposition cycle comprising:
feeding first precursors to the substrate;
applying a bias to the substrate; and
with the bias turned on, feeding second precursors to the substrate, wherein a deposition rate of the second precursors over the substrate is greater than a deposition rate of the second precursors over the mask layer.

### Claim 20 (depends on 19)

The method of claim 19, wherein the first precursors are silicon precursors, and the second precursors are H2O.