# US 12,191,142 B2 · Semiconductor structure and method for manufacturing semiconductor structure

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- Number: US 12,191,142 B2
- Document ID: US12191142B2
- Status: Granted
- Kind: B2
- Application number: 17/573,784
- Filed: 2022-01-12
- Published: 2023-01-26
- Granted: 2025-01-07
- Earliest claimed: 2021-07-22
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Kang You; Jie Bai
- Web page: https://patentgrep.com/patent/US12191142B2

## CPC

- H10P 14/6309: {of silicon in uncombined form, i.e. pure silicon}
- H10D 84/0144: {Manufacturing their gate insulating layers}
- H10D 84/0165: {the components including complementary IGFETs, e.g. CMOS devices}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/8314: {the IGFETs characterised by having gate insulating layers with different properties}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 50/283: {by chemical means}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0177: {the gate conductors having different materials or different implants}
- H10D 84/0181: {Manufacturing their gate insulating layers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83135: {the IGFETs characterised by having different gate conductor materials or different gate conductor implants}
- H10P 14/6322: {Formation by thermal treatments (formation by plasma treatment H10P14/6319)}
- H10P 50/642: {Chemical etching}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The method includes: providing a substrate including a core NMOS area, a core PMOS area and a peripheral NMOS area; performing oxidation treatment on the substrate in the core PMOS area to convert a thickness of a part of the substrate in the core PMOS area into an oxide layer; removing the oxide layer; forming a first semiconductor layer on the remaining substrate in the core PMOS area; forming a gate dielectric layer located on the first semiconductor layer and on the substrate in the core NMOS area and the peripheral NMOS area; and forming a gate on the gate dielectric layer.

## Claims

### Claim 1

A method for manufacturing a semiconductor structure, comprising:
providing a substrate comprising a core N-channel Metal Oxide Semiconductor (NMOS) area, a core P-channel Metal Oxide Semiconductor (PMOS) area and a peripheral NMOS area;
forming a first barrier layer on the surface of the substrate in the core PMOS area;
performing oxidation treatment on the substrate in the core PMOS area to convert a part of a thickness of the substrate in the core PMOS area into an oxide layer;
removing the first barrier layer in the core PMOS area and then removing the oxide layer, a thickness of the remaining substrate in the core PMOS area is less than a thickness of the substrate in the core NMOS area;
forming a first semiconductor layer on the remaining substrate in the core PMOS area, wherein a hole mobility in the first semiconductor layer is greater than a hole mobility in the substrate in the core PMOS area;
forming a gate dielectric layer located on the first semiconductor layer and on the substrate in the core NMOS area and the peripheral NMOS area; and
forming a gate on the gate dielectric layer.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein in a direction perpendicular to a surface of the substrate, a thickness of the oxide layer ranges from 10 Å to 200 Å.

### Claim 3 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein methods for the oxidation treatment comprise a thermal oxidation method, an in-situ water vapor generation oxidation method or an atomic group oxidation method.

### Claim 4 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein in the process step of forming the first barrier layer, the first barrier layer is also formed on the surface of the substrate in the core NMOS area and the peripheral NMOS area; and
before forming the oxide layer, the method further comprises:
forming a second barrier layer on a surface of the first barrier layer in the core NMOS area and the peripheral NMOS area, wherein the material of the second barrier layer is different from the material of the first barrier layer.

### Claim 5 (depends on 4)

The method for manufacturing a semiconductor structure of claim 4, further comprising:
after forming the first semiconductor layer, removing the second barrier layer, and retaining the first barrier layer in the core NMOS area and the peripheral NMOS area.

### Claim 6 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein the substrate further comprises a peripheral PMOS area; and after forming the first semiconductor layer, the method further comprises:
forming a second semiconductor layer on a surface of the substrate in the core NMOS area, the peripheral PMOS area and the peripheral NMOS area by a selective epitaxial process, wherein the material of the second semiconductor layer is the same as the material of the substrate.

### Claim 7 (depends on 6)

The method for manufacturing a semiconductor structure of claim 6, further comprising:
before forming the second semiconductor layer, forming a protective layer on a surface of the first semiconductor layer by a chemical oxidation method.

### Claim 8 (depends on 7)

The method for manufacturing a semiconductor structure of claim 7, wherein oxidation is performed by using hydrogen peroxide or ozone reagent, and in a direction perpendicular to the surface of the substrate, a thickness of the protective layer is less than or equal to 2 nm.

### Claim 9 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein the first semiconductor layer is formed by a selective epitaxial process; and the material of the first semiconductor layer comprises silicon germanium or germanium.

### Claim 10 (depends on 9)

The method for manufacturing a semiconductor structure of claim 9, wherein the material of the first semiconductor layer is silicon germanium, and in the silicon germanium, a mass percentage concentration of germanium element ranges from 5% to 50%.

### Claim 11 (depends on 1)

The method for manufacturing a semiconductor structure of claim 1, wherein the process step of forming the gate comprises:
forming a first work function layer on the gate dielectric layer in the core NMOS area, the core PMOS area and the peripheral NMOS area;
removing the first work function layer in the core NMOS area and the peripheral NMOS area;
forming a second work function layer on the gate dielectric layer in the core NMOS area and the peripheral NMOS area, wherein the second work function layer is further located on a surface of the first work function layer; and
forming a gate electrode layer on the second work function layer.