# US 12,191,135 B2 · Two transistor gain cell memory with indium gallium zinc oxide

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,191,135 B2
- Document ID: US12191135B2
- Status: Granted
- Kind: B2
- Application number: 17/132,908
- Filed: 2020-12-23
- Published: 2021-05-20
- Granted: 2025-01-07
- Earliest claimed: 2020-12-23
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Shigeki Tomishima
- Web page: https://patentgrep.com/patent/US12191135B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- H10B 12/00: Dynamic random access memory [DRAM] devices
- H10B 12/01: {Manufacture or treatment}
- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 62/402: {Amorphous materials}
- H10D 62/80: characterised by the materials
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)}
- H10P 14/3454: {Amorphous}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10B 12/05: {Making the transistor}
- H10D 30/674: {characterised by the active materials}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10B: ELECTRONIC MEMORY DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

An example two transistor (2T) gain cell memory with indium-gallium-zinc-oxide (IGZO) transistors. Examples include IGZO transistors included in a dynamic random access memory (DRAM) cell. The IGZO transistors included in the DRAM cell are described as being formed or created in a back end (BE) metal process stack of an integrated circuit chip or die.

## Claims

### Claim 1

A two-transistor dynamic random access memory (DRAM) cell comprising:
a read bit line;
a write bit line;
a read word line;
a write word line;
a first indium-gallium-zinc-oxide (IGZO) transistor with a first gate region coupled to the write word line, a first controlled node region coupled to the write bit line, and a second controlled node region; and
a second IGZO transistor with a second gate region, a third controlled node region coupled to the read word line, and a fourth controlled node region coupled to the read bit line, the second gate region of the second IGZO transistor coupled to the second controlled node region of the first IGZO transistor,
wherein the first IGZO transistor is included in a first layer created in a back end (BE) metal process stack of an integrated circuit chip and the second IGZO transistor is included in a second layer created in the BE metal process stack.

### Claim 2 (depends on 1)

The two-transistor DRAM cell of claim 1, the first and second IGZO transistors comprising n-channel metal-oxide-semiconductor (NMOS) type transistors.

### Claim 3 (depends on 1)

The two-transistor DRAM cell of claim 1, comprising the integrated circuit chip to include a processor, the two-transistor DRAM cell included in a memory array arranged to be an on-die last-level cache for the processor.

### Claim 4 (depends on 3)

The two-transistor DRAM cell of claim 3, the memory array created in the BE metal process stack and the processor created in a front end silicone process stack of the integrated circuit chip.

### Claim 5

A system comprising:
an integrated circuit chip; and
a two-transistor dynamic random access memory (DRAM) cell that includes:
a first indium-gallium-zinc-oxide (IGZO) transistor with a first gate region coupled to a write word line, a first controlled node region coupled to a write bit line, and a second controlled node region; and
a second IGZO transistor with a second gate region, a third controlled node region coupled to a read word line, and a fourth controlled node region coupled to a read bit line, the second gate region of the second IGZO transistor coupled to the second controlled node region of the first IGZO transistor,
wherein the first IGZO transistor is included in a first layer created in a back end (BE) metal process stack of the integrated circuit chip and the second IGZO transistor is included in a second layer created in the BE metal process stack.

### Claim 6 (depends on 5)

The system of claim 5, the first and second IGZO transistors comprising n-channel metal-oxide-semiconductor (NMOS) type transistors.

### Claim 7 (depends on 5)

The system of claim 5, comprising the integrated circuit chip to include a processor, the two-transistor DRAM cell included in a memory array arranged to be an on-die last-level cache for the processor.

### Claim 8 (depends on 7)

The system of claim 7, the memory array created in the BE metal process stack and the processor created in a front end silicone process stack of the integrated circuit chip.