# US 12,191,056 B2 · Buried thermistor and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,191,056 B2 - Document ID: US12191056B2 - Status: Granted - Kind: B2 - Application number: 17/852,162 - Filed: 2022-06-28 - Published: 2023-11-23 - Granted: 2025-01-07 - Earliest claimed: 2022-05-20 - Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd.; Avary Holding (Shenzhen) Co., Limited.; Garuda Technology Co., Ltd. - Applicants: HongQiSheng Precision Electronics (QinHuangdao) Co., Ltd.; Avary Holding (Shenzhen) Co., Ltd.; Garuda Technology Co., Ltd. - Inventors: Jian Wang; Jun Dai; Xiao-Juan Zhang - Web page: https://patentgrep.com/patent/US12191056B2 ## CPC - H01C 7/008: {Thermistors (H01C7/02 - H01C7/06 take precedence)} - H01C 1/142: the terminals or tapping points being coated on the resistive element - H01C 7/006: {Thin film resistors} - H01C 17/006: {adapted for manufacturing resistor chips} - H01C: RESISTORS ## Abstract A buried thermistor includes a lower substrate, an upper substrate, and a number of thermistor stacks. Each thermistor stack includes two resistor subjects. Each resistor subject includes a base layer, a medium layer, a metal layer, a resistor layer, a nanometal layer, and a conductive layer. Applicable material of the resistor layer becomes more diverse by disposing the number of thermistor stacks, and the buried thermistor shows variable thermal sensitivity. ## Claims ### Claim 1 A buried thermistor, comprising: a lower substrate; an upper substrate disposed above the lower substrate; and a plurality of thermistor stacks disposed between the upper substrate and the lower substrate, wherein each of the plurality of thermistor stacks comprises two resistor subjects, a through-hole via separates the two resistor subjects, and each of the resistor subjects comprises: a base layer; a medium layer disposed over the base layer; a resistor layer disposed over the medium layer; a metal layer disposed on the resistor layer; a nanometal layer disposed on a portion of the metal layer and a terminal portion of the resistor layer, wherein the metal layer is not disposed on the terminal portion of the resistor layer; and a conductive layer, covering a portion of an upper surface of the nanometal layer and extending to a sidewall of the nanometal layer and a sidewall of the resistor layer, wherein the terminal portions of the resistor layers of the two resistor subjects surround the through-hole via. ### Claim 2 (depends on 1) The buried thermistor of claim 1, wherein the upper substrate and the lower substrate comprise a substrate layer, a metal base layer and a cover film, respectively. ### Claim 3 (depends on 2) The buried thermistor of claim 2, wherein the cover film of the lower substrate has at least an opening. ### Claim 4 (depends on 1) The buried thermistor of claim 1, wherein the conductive layer extends to a portion of a sidewall of the medium layer. ### Claim 5 (depends on 1) The buried thermistor of claim 1, further comprises: a plurality of adhesive layer disposed between the upper substrate, the lower substrate and the plurality of thermistor stacks. ### Claim 6 (depends on 1) The buried thermistor of claim 1, wherein the metal layer of one of the resistor subjects of at least one of the plurality of thermistor stacks comprises a recess, and the recess is adjacent to the nanometal layer. ### Claim 7 (depends on 1) The buried thermistor of claim 1, further comprises: a plurality of through-hole metal, connected the plurality of thermistor stacks and the lower substrate. ### Claim 8 (depends on 1) The buried thermistor of claim 1, wherein the through-hole vias of at least two of the plurality of thermistor stacks have different widths. ### Claim 9 (depends on 1) The buried thermistor of claim 1, wherein the through-hole vias of at least two of the plurality of thermistor stacks have the same widths. ### Claim 10 (depends on 1) The buried thermistor of claim 1, wherein the base layer has a gap, and the gap is located directly below the nanometal layer, but not completely below the conductive layer. ### Claim 11 A method of fabricating a buried thermistor, comprises: fabricating a plurality of thermistor stacks, comprises: forming a stack layer, wherein the stack layer comprises a medium layer, a resistor layer and a metal layer, and the metal layer comprises a recess; coating a nanometal layer within the recess and on a portion of the metal layer surrounding the recess; forming a through-hole via in the nanometal layer, wherein the through-hole via extends through the nanometal layer and the stack layer, thereby separating the nanometal layer and the stack layer into a first portion and a second portion; depositing two conductive layers, respectively, on a portion of a top surface of the nanometal layer of the first portion and the second portion, and extending on a sidewall of the first portion and a side wall of the second portion, respectively; and laminating a base layer on bottom of the first portion and the second portion, respectively; fabricating an upper substrate and a lower substrate; and binding the upper substrate, the plurality of thermistor stacks and the lower substrate, wherein the plurality of thermistor stacks are located between the upper substrate and the lower substrate. ### Claim 12 (depends on 11) The method of claim 11, wherein forming the stack layer comprises: forming a resistor layer over a medium layer; forming a metal layer over the resistor layer; and forming the recess in the metal layer. ### Claim 13 (depends on 12) The method of claim 12, wherein forming the stack layer further comprises: forming a laminating layer under the medium layer, wherein after depositing the two conductive layer, respectively, removing the laminating layer. ### Claim 14 (depends on 11) The method of claim 11, wherein after laminating the base layer, the method further comprises: forming a gap within the base layer, and the gap is located directly below the nanometal layer. ### Claim 15 (depends on 11) The method of claim 11, further comprises: forming an upper cover film on the upper substrate; and forming a lower cover film on the lower substrate, wherein a bottom of the lower cover film comprises two openings, and the two openings expose the lower substrate.