# US 12,190,992 B2 · Command processing circuit and data processing circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,992 B2 - Document ID: US12190992B2 - Status: Granted - Kind: B2 - Application number: 18/150,803 - Filed: 2023-01-06 - Published: 2023-11-16 - Granted: 2025-01-07 - Earliest claimed: 2022-05-13 - Assignees: Changxin Memory Technologies, Inc. - Applicants: Changxin Memory Technologies, Inc. - Inventors: Liping Chang - Web page: https://patentgrep.com/patent/US12190992B2 ## CPC - G11C 7/109: {Control signal input circuits} - G11C 7/00: Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) - G11C 7/1093: {Input synchronization} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 7/1087: {Data input latches} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Embodiments provide a command processing circuit and a data processing circuit, including a plurality of flip-flops. An output terminal of a former flip-flop is connected to an input terminal of a latter flip-flop. The flip-flop is configured to sample, according to switching of a data strobe signal, an internal write command inputted into the command processing circuit to obtain a sampling command, to sample data. An output terminal of a target flip-flop is connected to a target terminal of a first flip-flop, the target flip-flop is a flip-flop whose time of outputting an active level overlaps target time, where the target time is start time and/or end time of a pulse in the internal write command. The target flip-flop is configured to reset the internal write command in the first flip-flop by outputting the active level. ## Claims ### Claim 1 A command processing circuit, comprising a plurality of flip-flops arranged in sequence, an output terminal of a former one of the plurality of flip-flops being connected to an input terminal of a latter one of the plurality of flip-flops, the plurality of flip-flops being configured to sample, according to switching of a data strobe signal, an internal write command inputted into the command processing circuit to obtain a sampling command, the sampling command being configured for sampling data; wherein an output terminal of a target flip-flop in the plurality of flip-flops is connected to a target terminal of a first one of the plurality of flip-flops, the target flip-flop being a flip-flop whose time of outputting an active level overlaps target time, the target time being start time and/or end time of a pulse in the internal write command; and wherein the target flip-flop is configured to reset the internal write command in the first flip-flop by outputting the active level. ### Claim 2 (depends on 1) The command processing circuit according to claim 1, wherein the target terminal comprises at least one of a reset terminal and an input terminal. ### Claim 3 (depends on 2) The command processing circuit according to claim 2, wherein when the target terminal comprises the input terminal, the command processing circuit further comprises a logic processing circuit; wherein one input terminal of the logic processing circuit is connected to the output terminal of the target flip-flop, other input terminal of the logic processing circuit being configured to input the internal write command, and an output terminal of the logic processing circuit being connected to an input terminal of the first flip-flop; and wherein the logic processing circuit is configured to input reset data to the first flip-flop when the target flip-flop outputs the active level and the internal write command is the active level. ### Claim 4 (depends on 3) The command processing circuit according to claim 3, wherein the logic processing circuit comprises an inverter and an AND gate, the output terminal of the target flip-flop being connected to an input terminal of the inverter, an output terminal of the inverter being connected to one input terminal of the AND gate, and other input terminal of the AND gate being configured to input the internal write command. ### Claim 5 (depends on 3) The command processing circuit according to claim 3, wherein when number of the target flip-flops is two, an output terminal of one of the two target flip-flops is connected to the reset terminal of the first flip-flop, and an output terminal of the other one of the two target flip-flops is connected to one input terminal of the logic processing circuit. ### Claim 6 (depends on 3) The command processing circuit according to claim 3, wherein the target flip-flop comprises at least one of a second one of the plurality of flip-flops and a sixth one of the plurality of flip-flops. ### Claim 7 (depends on 6) The command processing circuit according to claim 6, wherein an output terminal of the second flip-flop is connected to the input terminal of the first flip-flop, and an output terminal of the sixth flip-flop is connected to one input terminal of the logic processing circuit. ### Claim 8 (depends on 1) The command processing circuit according to claim 1, wherein a pulse width of the internal write command is one or two clock cycles. ### Claim 9 (depends on 8) The command processing circuit according to claim 8, wherein an overlap duration between the time of outputting the active level by the target flip-flop and the target time is less than half of the pulse width. ### Claim 10 (depends on 1) The command processing circuit according to claim 1, wherein the active level is a high level. ### Claim 11 (depends on 1) The command processing circuit according to claim 1, wherein any adjacent two of the plurality of flip-flops use data strobe signals opposite in phase. ### Claim 12 (depends on 1) The command processing circuit according to claim 1, wherein number of the plurality of flip-flops is seven, output of a seventh one of the plurality of flip-flops being used as the sampling command. ### Claim 13 (depends on 1) A data processing circuit, comprising a data sampling circuit and the command processing circuit according to claim 1, the data sampling circuit being configured to sample data according to a sampling command outputted by the command processing circuit. ### Claim 14 (depends on 13) The data processing circuit according to claim 13, wherein the data processing circuit further comprises a strobe signal receiving circuit, the strobe signal receiving circuit being connected to the command processing circuit via a delay circuit, the delay circuit being configured to delay a data strobe signal received by the strobe signal receiving circuit and send the delayed data strobe signal to the command processing circuit. ### Claim 15 (depends on 14) The data processing circuit according to claim 14, wherein the data processing circuit further comprises a command generation circuit connected to the command processing circuit, the command generation circuit being configured to generate the internal write command and send the internal write command to the command processing circuit.