# US 12,190,989 B2 · Data output buffer and semiconductor apparatus including the same

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- Number: US 12,190,989 B2
- Document ID: US12190989B2
- Status: Granted
- Kind: B2
- Application number: 18/334,261
- Filed: 2023-06-13
- Published: 2023-10-12
- Granted: 2025-01-07
- Earliest claimed: 2021-03-23
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Kyu Dong Hwang; Bo Ram Kim; Dae Han Kwon
- Web page: https://patentgrep.com/patent/US12190989B2

## CPC

- G11C 7/1039: {using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers}
- G11C 7/1057: {Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- G11C 29/022: {in I/O circuitry}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/50008: {of impedance}
- H03K 19/0005: {Modifications of input or output impedance}
- H03K 19/01742: {by means of a pull-up or down element}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A data output buffer includes a first driver configured to drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to an impedance calibration code and a second driver configured to perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to the impedance calibration code.

## Claims

### Claim 1

A data output buffer comprising:
a first driver configured to directly receive an impedance calibration code, drive a data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to the impedance calibration code;
a second driver configured to directly receive emphasis signals, perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to a selection code and the emphasis signals; and
a selection circuit configured to output one of a fixing code and the impedance calibration code as the selection code according to a selection signal,
wherein the first driver and the second driver are coupled to the data I/O pad directly.

### Claim 2 (depends on 1)

The data output buffer of claim 1, wherein the first driver includes:
a pull-up driver configured to drive the data I/O pad according to a first data signal of the input signal and allow the data drivability to be controlled according to a first impedance calibration code of the impedance calibration code; and
a pull-down driver configured to drive the data I/O pad according to a second data signal of the input signal and allow the data drivability to be controlled according to a second impedance calibration code of the impedance calibration code.

### Claim 3 (depends on 1)

The data output buffer of claim 1, wherein the second driver includes:
a pull-up driver configured to perform the de-emphasis operation according to a first emphasis signal of the emphasis signals and allow the de-emphasis drivability to be controlled according to all code bits of a first selection code of the selection code; and
a pull-down driver configured to perform the de-emphasis operation according to a second emphasis signal of the emphasis signals and allow the de-emphasis drivability to be controlled according to all code bits of a second selection code of the selection code.

### Claim 4 (depends on 1)

The data output buffer of claim 1, wherein the second driver includes:
a plurality of pull-up driving circuits configured to commonly receive a first emphasis signal the emphasis signals and receive all code bits of a first selection code of the selection code bit by bit, respectively; and
a plurality of pull-down driving circuits configured to commonly receive a second emphasis signal of the emphasis signals and receive all code bits of a second selection code of the selection code bit by bit, respectively.

### Claim 5 (depends on 1)

The data output buffer of claim 1, wherein the second driver includes:
a pull-up driver configured to perform the de-emphasis operation according to a first emphasis signal of the emphasis signals and allow the de-emphasis drivability to be controlled according to partial code bits of a first selection code of the selection code; and
a pull-down driver configured to perform the de-emphasis operation according to a second emphasis signal of the emphasis signals and allow the de-emphasis drivability to be controlled according to partial code bits of a second selection code of the selection code.

### Claim 6 (depends on 1)

The data output buffer of claim 1, wherein the second driver includes:
a plurality of pull-up driving circuits configured to commonly receive a first emphasis signal of the emphasis signals and receive partial code bits of a first selection code of the selection code bit by bit, respectively; and
a plurality of pull-down driving circuits configured to commonly receive a second emphasis signal of the emphasis signals and receive partial code bits of a second selection code of the selection code bit by bit, respectively.

### Claim 7 (depends on 2)

The data output buffer of claim 2, wherein the second driver includes:
a pull-up driver configured to perform the de-emphasis operation by raising a voltage level of the data I/O pad when the pull-down driver of the first driver drives the data I/O pad as a low level; and
a pull-down driver configured to perform the de-emphasis operation by lowering the voltage level of the data I/O pad when the pull-up driver of the first driver drives the data I/O pad as a high level.

### Claim 8

A semiconductor apparatus comprising:
a memory region configured to output read data through a data input/output (I/O) pad according to a read command and configured to store write data that is input through the data I/O pad according to a write command;
an impedance calibration circuit configured to adjust a value of an impedance calibration code based on an impedance of an external resistor;
a first driver configured to directly receive the impedance calibration code. drive the data input/output (I/O) pad according to an input signal and allow data drivability to be controlled according to the impedance calibration code;
a second driver configured to directly receive emphasis signals, perform a de-emphasis operation on the data I/O pad and allow de-emphasis drivability to be controlled according to a selection code and the emphasis signals; and
a selection circuit configured to output one of a fixing code and the impedance calibration code as the selection code according to a selection signal,
wherein the first driver and the second driver are coupled to the data I/O pad directly.

### Claim 9 (depends on 8)

The semiconductor apparatus of claim 8, wherein the first driver includes:
a pull-up driver configured to drive the data I/O pad according to a first data signal of the input signal and allow the data drivability to be controlled according to a first impedance calibration code of the impedance calibration code; and
a pull-down driver configured to drive the data I/O pad according to a second data signal of the input signal and allow the data drivability to be controlled according to a second impedance calibration code of the impedance calibration code.

### Claim 10 (depends on 8)

The semiconductor apparatus of claim 8, wherein the second driver includes:
a pull-up driver configured to perform the de-emphasis operation according to a first emphasis signal of the emphasis signals and allow the de- emphasis drivability to be controlled according to all code bits or partial code bits of a first selection code of the selection code; and
a pull-down driver configured to perform the de-emphasis operation according to a second emphasis signal of the emphasis signals and allow the de-emphasis drivability to be controlled according to all code bits or partial code bits of a second selection code of the selection code.

### Claim 11 (depends on 8)

The semiconductor apparatus of claim 8, wherein the second driver includes:
a plurality of pull-up driving circuits configured to commonly receive a first emphasis signal of the emphasis signals and receive all code bits or partial code bits of a first selection code of the selection code bit by bit, respectively; and
a plurality of pull-down driving circuits configured to commonly receive a second emphasis signal of the emphasis signals and receive all code bits or partial code bits of a second selection code of the selection code bit by bit, respectively.

### Claim 12 (depends on 9)

The semiconductor apparatus of claim 9, wherein the second driver includes:
a pull-up driver configured to perform the de-emphasis operation by raising a voltage level of the data I/O pad when the pull-down driver of the first driver drives the data I/O pad as a low level; and
a pull-down driver configured to perform the de-emphasis operation by lowering the voltage level of the data I/O pad when the pull-up driver of the first driver drives the data I/O pad as a high level.