# US 12,190,987 B2 · Method for configuring multiple input-output channels

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- Number: US 12,190,987 B2
- Document ID: US12190987B2
- Status: Granted
- Kind: B2
- Application number: 17/962,253
- Filed: 2022-10-07
- Published: 2023-02-02
- Granted: 2025-01-07
- Earliest claimed: 2020-08-31
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Dean E. Walker; Tony Brewer
- Web page: https://patentgrep.com/patent/US12190987B2

## CPC

- G06F 13/1668: {Details of memory controller}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F 9/30101: {Special purpose registers}
- G06F 13/1694: {Configuration of memory controller to different memory types}
- G11C 7/1069: {I/O lines read out arrangements}
- G11C 7/1096: {Write circuits, e.g. I/O line write drivers}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/641: {Adaptable interconnections, e.g. fuses or antifuses}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C 2207/105: Aspects related to pads, pins or terminals
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method includes setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets; and programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet.

## Claims

### Claim 1

A method comprising:
setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets; and
programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet, including:
reading a column capability register of a column of the second chiplet to determine if the order of the input-output channels of the column is reversable; and
writing a column configuration register of the column of the second chiplet to reverse the order of the input-output channels of the column.

### Claim 2 (depends on 1)

The method of claim 1, including grouping together the reversed input-output channels of the second chiplet into a channel that spans multiple columns.

### Claim 3 (depends on 1)

The method of claim 1, including:
reading a bit vector indicating that the column supports multi-column reversal across a number of columns; and
reversing an order of multiple columns of the second chiplet according to the bit vector.

### Claim 4 (depends on 1)

The method of claim 1, including:
reading the column capability register of the column to determine if the column supports multi-column reversal; and
writing the column configuration register to reverse an order of input-output channels of multiple columns of the second chiplet to match an order of input-output channels of multiple columns of the first chiplet.

### Claim 5 (depends on 1)

The method of claim 1, including:
reading the channel capability register of the channel of the column of the second chiplet to determine if the channel supports bonding to another channel; and
writing the channel configuration register of the channel to bond the channel with one or more other channels of the second chiplet into a wider combined channel interface.

### Claim 6 (depends on 5)

The method of claim 5, wherein the programming of the second chiplet includes writing channel configuration registers of multiple channels of the second chiplet to bond the multiple channels into a combined channel that is included in multiple columns.

### Claim 7 (depends on 5)

The method of claim 5, wherein the programming of the second chiplet further includes writing a column configuration register to reverse the order of channels of the multiple columns.

### Claim 8 (depends on 5)

The method of claim 5, wherein writing a value of X into the channel configuration register combines the channel and X−1 other channels into the combined channel, wherein X is a positive integer greater than one.

### Claim 9 (depends on 1)

The method of claim 1, wherein the programming of the second chiplet includes:
reading a bit vector of an input-output channel of the second chiplet to determine if the input-output channel supports bonding across a number of input-output channels indicated by the bit vector; and
bonding multiple input-output channels of the second chiplet according to the bit vector.

### Claim 10

A non-transitory machine-readable medium including instructions that, when executed by a system, cause the system to perform operations comprising:
setting an order of channels of a column of a first chiplet of multiple chiplets of the system, wherein one or more chiplets of the multiple chiplets include input-output channels arranged as one or more columns at a periphery of the chiplets;
writing a value to a channel configuration register of the first chiplet to bond channels of the column of the first chiplet into a combined channel of the first chiplet; and
writing a value to a column configuration register of a second chiplet of the multiple chiplets to reverse an order of channels of a column of the second chiplet to match the order of channels of the column of the first chiplet, and to bond one or more reversed order channels of the column of the second chiplet into a combined channel of the second chiplet to form an interface with the combined channel of the first chiplet.

### Claim 11 (depends on 10)

The non-transitory machine-readable medium of claim 10, including instructions that cause the system to perform operations including writing channel configuration registers of multiple channels of the second chiplet to bond the multiple channels into a combined channel that is included in multiple columns.

### Claim 12 (depends on 10)

The non-transitory machine-readable medium of claim 10, including instructions that cause the system to perform operations including writing a column configuration register to reverse the order of channels of the multiple columns.

### Claim 13 (depends on 10)

The non-transitory machine-readable medium of claim 10, including instructions that cause the system to perform operations including writing a value of X into the channel configuration register combines the channel and X−1 other channels into the combined channel, wherein X is a positive integer greater than one.

### Claim 14 (depends on 10)

The non-transitory machine-readable medium of claim 10, including instructions that cause the system to perform operations including:
reading a bit vector of an input-output channel of the second chiplet to determine if the input-output channel supports bonding across a number of input-output channels indicated by the bit vector; and
bonding multiple input-output channels of the second chiplet according to the bit vector.

### Claim 15 (depends on 10)

The non-transitory machine-readable medium of claim 10, including instructions that cause the system to perform operations including:
reading a column capability register of the second chiplet to determine if the column supports multi-column reversal; and
writing a value to the column configuration register to reverse an order of channels of multiple columns of the second chiplet to match an order of channels of multiple columns of the first chiplet.

### Claim 16 (depends on 10)

The non-transitory machine-readable medium of claim 10, including instructions that cause the system to perform operations including:
reading a column capability register of a column of the second chiplet to determine if the order of the input-output channels of the column is reversable; and
writing a value to the column configuration register of the column of the second chiplet to reverse the order of the input-output channels of the column.

### Claim 17 (depends on 16)

The non-transitory machine-readable medium of claim 16, including instructions that cause the system to perform operations including grouping together the reversed input-output channels of the second chiplet into a channel that spans multiple columns.

### Claim 18 (depends on 16)

The non-transitory machine-readable medium of claim 16, including:
reading a bit vector indicating that the column supports multi-column reversal across a number of columns; and
reversing an order of multiple columns of the second chiplet according to the bit vector.