Sense amplifier circuit, memory device, and operation method thereof

A sense amplifier circuit, comprising:

• an amplification circuit, comprising:
• a first inverting amplifier and a second inverting amplifier, wherein an input of the first inverting amplifier is connected to an output of the second inverting amplifier at a first node, and an input of the second inverting amplifier is connected to an output of the first inverting amplifier at a second node, wherein the first inverting amplifier comprises a first transistor and a second transistor, a gate terminal of the first transistor and a gate terminal of the second transistor are directly connected together to form the input of the first inverting amplifier at the first node;
• the second inverting amplifier comprises a third transistor and a fourth transistor, and a gate terminal of the third transistor and a gate terminal of the fourth transistor are directly connected together to form the input of the second inverting amplifier at the second node;
• and
• a compensation circuit coupled to the amplification circuit and configured to:
• in a equalization stage, control a first bitline to connect to the first node and the second node, and control a second bitline to connect to the first node and the second node;
• in an offset compensation stage, switch off a connection between the first bitline and the second node, and switch off a connection between the second bitline and the first node, at least remain on a connection between the first bitline and the first node or remain on a connection between the second bitline and the second node, wherein the compensation circuit is configured to conduct a charging operation to charge at least one of the first bitline and the second bitline,
• wherein, at the end of the charging operation, a voltage difference between near-ends of the first bitline and the second bitline is larger than the input-referred offset voltage of the amplification circuit.

A sense amplifier circuit, comprising:

• an amplification circuit, comprising:
• a first inverting amplifier and a second inverting amplifier, wherein an input of the first inverting amplifier is connected to an output of the second inverting amplifier at a first node, and an input of the second inverting amplifier is connected to an output of the first inverting amplifier at a second node, wherein the first inverting amplifier comprises a first transistor and a second transistor, a gate terminal of the first transistor and a gate terminal of the second transistor are directly connected together to form the input of the first inverting amplifier at the first node;
• the second inverting amplifier comprises a third transistor and a fourth transistor, and a gate terminal of the third transistor and a gate terminal of the fourth transistor are directly connected together to form the input of the second inverting amplifier at the second node;
• and
• a compensation circuit coupled to the amplification circuit and configured to:
• in an offset compensation stage, switch off a connection between the first bitline and the second node, and switch off a connection between the second bitline and the first node, at least remain on a connection between the first bitline and the first node or remain on a connection between the second bitline and the second node, wherein the first inverting amplifier and the second inverting amplifier are cross-coupled during the offset compensation stage.

A sense amplifier circuit, comprising:

• an amplification circuit, comprising:
• a first inverting amplifier connected to a first bitline;
• and
• a second inverting amplifier connected to a second bitline, wherein the amplification circuit is configured to amplify a voltage signal applied between the first bitline and the second bitline;
• and
• a compensation circuit coupled to the amplification circuit and configured to compensate an input-referred offset voltage of the amplification circuit, wherein the compensation circuit is configured to conduct a charging operation to charge at least one of the first bitline and the second bitline,
• and wherein, at the end of the charging operation, a voltage difference between near-ends of the first bitline and the second bitline is larger than the input-referred offset voltage of the amplification circuit;
• wherein after a distribution of charges on bitlines is settled, a compensation voltage generated by charges distributed on the first bitline and the second bitline is within ±10% of an input-referred offset voltage of an amplification circuit.