# US 12,190,981 B2 · Memory array having error checking and correction circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,981 B2 - Document ID: US12190981B2 - Status: Granted - Kind: B2 - Application number: 17/866,558 - Filed: 2022-07-18 - Published: 2024-01-18 - Granted: 2025-01-07 - Earliest claimed: 2022-07-18 - Assignees: Winbond Electronics Corp. - Applicants: Winbond Electronics Corp. - Inventors: Yao-Ting Tsai; Che-Fu Chuang - Web page: https://patentgrep.com/patent/US12190981B2 ## CPC - G11C 29/72: {with optimized replacement algorithms} - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 29/785: {with redundancy programming schemes} - H10B 41/10: characterised by the top-view layout - H10B 41/42: Simultaneous manufacture of periphery and memory cells - G11C 8/14: Word line organisation; Word line lay-out - G11C 2029/0411: {Online error correction} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks. ## Claims ### Claim 1 A memory array comprising: a repeating unit comprising: a plurality of memory blocks, each of the plurality of memory blocks comprising a plurality of data storage regions; and a plurality of groups of word lines extending across one of the plurality of memory blocks and being connected to a plurality of overlying signal lines through a plurality of groups of first word line contact regions in the plurality of memory blocks and a plurality of second word line contact regions between the plurality of memory blocks, wherein a peripheral memory block in the plurality of memory blocks further comprises an error checking and correction circuit region, and an error checking and correction circuit in the error checking and correction circuit region is configured to perform error checking and correction for the plurality of data storage regions of each of the plurality of memory blocks in the repeating unit. ### Claim 2 (depends on 1) The memory array according to claim 1, wherein each of the groups of word lines continuously extends through a first word line contact region in the plurality of groups of first word line contact regions, and adjacent two groups of word lines in the plurality of groups of word lines are spaced apart from each other at one of the plurality of second word line contact regions. ### Claim 3 (depends on 1) The memory array according to claim 1, wherein the plurality of data storage regions in each of the memory blocks are spaced apart from each other by a group of first word line contact regions in the plurality of groups of first word line contact regions. ### Claim 4 (depends on 3) The memory array according to claim 3, wherein a plurality of active regions in each of the memory blocks are distributed in the plurality of data storage regions and the group of first word line contact regions in the plurality of groups of first word line contact regions in each of the memory blocks. ### Claim 5 (depends on 4) The memory array according to claim 4, wherein a plurality of word line contact structures electrically connect the plurality of groups of word lines and the plurality of signal lines, and a first group of word line contact structures in the plurality of word line contact structures is located in a first word line contact region in the plurality of groups of first word line contact regions, and are alternately arranged on both sides of one of the plurality of active regions along a direction intersecting an extension direction of the plurality of groups of word lines. ### Claim 6 (depends on 5) The memory array according to claim 5, wherein adjacent two of the first group of word line contact structures are spaced apart from each other in a first direction and a second direction intersecting the first direction. ### Claim 7 (depends on 5) The memory array according to claim 5, wherein a second group of word line contact structures in the plurality of word line contact structures is located in one of the plurality of second word line contact regions, and adjacent two of the second group of word line contact structures are spaced apart from each other in a first direction and a second direction intersecting the first direction. ### Claim 8 (depends on 1) The memory array according to claim 1, wherein a plurality of drain/source contact structures are disposed in the plurality of memory blocks, and the plurality of drain/source contact structures are not distributed into the plurality of groups of first word line contact regions. ### Claim 9 (depends on 8) The memory array according to claim 8, further comprising a plurality of additional signal lines connected to the plurality of drain/source contact structures and being parallel to a plurality of active regions in the plurality of memory blocks. ### Claim 10 (depends on 1) The memory array according to claim 1, wherein the peripheral memory block in the plurality of memory blocks further comprises a third word line contact region located between the error checking and correction circuit region and the plurality of data storage regions, and a group of word lines in the plurality of groups of word lines is further connected to the plurality of overlying signal lines through a plurality of word line contact structures in the third word line contact region. ### Claim 11 (depends on 10) The memory array according to claim 10, wherein a plurality of active regions in the peripheral memory block of the plurality of memory blocks are further distributed in the third word line contact region, and a plurality of drain/source contact structures in the peripheral memory block in the plurality of memory blocks are not distributed into the third word line contact region. ### Claim 12 (depends on 10) The memory array according to claim 10, further comprising a fourth word line contact region adjoined to the error checking and correction circuit region of the peripheral memory block in the plurality of memory blocks, the group of word lines in the plurality of groups of word lines is connected to the plurality of signal lines through a plurality of word line contact structures in the fourth word line contact region, and the error checking and correction circuit region is located between the third word line contact region and the fourth word line contact region. ### Claim 13 (depends on 12) The memory array according to claim 12, wherein the group of word lines in the plurality of groups of word lines has a plurality of long distal-end line segments and a plurality of short distal-end line segments located in the fourth word line contact region, the plurality of long distal-end line segments and the plurality of short distal-end line segments are alternately arranged along a direction intersecting an extension direction of the plurality of groups of word lines. ### Claim 14 (depends on 1) The memory array according to claim 1, wherein a plurality of dummy active regions are disposed in each of the second word line contact regions, and a conductivity type and an extension direction of the plurality of dummy active regions are respectively the same as a conductivity type and an extension direction of a plurality of active regions in each of the memory blocks. ### Claim 15 (depends on 1) The memory array according to claim 1, wherein the peripheral memory block in the plurality of memory blocks further comprises a redundant cell region, wherein the redundant cell region has a redundant cell configured to replace a damaged memory cell in the plurality of memory blocks, and wherein memory blocks other than the peripheral memory block in the plurality of memory blocks do not comprise the redundant cell region configured to replace the damaged memory cell. ### Claim 16 (depends on 1) The memory array according to claim 1, wherein the plurality of signal lines extend across the plurality of memory blocks, and wherein the plurality of signal lines are parallel to the plurality of groups of word lines. ### Claim 17 A memory array comprising: a plurality of memory blocks defined by a plurality of wells, wherein the plurality of wells are disposed in a substrate and arranged in parallel, and each of the memory blocks comprises a plurality of data storage regions; and a plurality of well taps located on the substrate, extending along a single outer contour surrounding the plurality of wells, and electrically connected to the plurality of wells, wherein the plurality of well taps comprise: two first well taps respectively surrounding two peripheral wells in the plurality of wells on three sides; and a plurality of second well taps each having two line segments separated from each other, the plurality of second well taps extending along opposite sides of a plurality of central wells in the plurality of wells. ### Claim 18 (depends on 17) The memory array according to claim 17, wherein the plurality of well taps do not extend to a region between the plurality of wells.