# US 12,190,979 B2 · Dynamic random access memory built-in self-test power fail mitigation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,979 B2 - Document ID: US12190979B2 - Status: Granted - Kind: B2 - Application number: 18/373,658 - Filed: 2023-09-27 - Published: 2024-01-18 - Granted: 2025-01-07 - Earliest claimed: 2020-02-04 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Bill Nale - Web page: https://patentgrep.com/patent/US12190979B2 ## CPC - G11C 29/46: Test trigger logic - G06F 11/3037: {where the computing system component is a memory, e.g. virtual memory, cache (accessing, addressing or allocating within memory systems or architectures G06F12/00; checking stores for correct operation G11C29/00)} - G06F 11/3058: {Monitoring arrangements for monitoring environmental properties or parameters of the computing system or of the computing system component, e.g. monitoring of power, currents, temperature, humidity, position, vibrations (thermal management in cooling arrangements of a computing system G06F1/206)} - G06F 11/326: {for error or online/offline status} - G11C 29/021: {in voltage or current generators} - G11C 29/022: {in I/O circuitry} - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 29/4401: {for self repair} - G11C 29/76: {using address translation or modifications} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Self-test and repair of memory cells is performed in a memory integrated circuit by two separate processes initiated by a memory controller communicatively coupled to the memory integrated circuit. To ensure that the repair process is completed in the event of an unexpected power failure, a first process is initiated by the memory controller to perform a memory Built-in Self Test (mBIST) in the memory integrated circuit and a second process is initiated by the memory controller after the mBIST has completed to perform repair of faulty memory cells detected during the MBIST process. The memory controller does not initiate the repair process if a power failure has been detected. In addition, a repair time associated with the repair process is selected such that the repair time is sufficient to complete the repair process while power is stable, if a power failure occurs after the repair process has been started. ## Claims ### Claim 1 A synchronous dynamic random access memory (SDRAM) device, comprising: one or more mode registers, each mode register having a plurality of bits; a memory array; Memory Built-in Self Test circuitry to use patterns to test the memory array, the Memory Built-in Self Test circuitry to store a status of the test of the memory array in a first mode register; and repair circuitry to perform a hard repair of a first portion of faulty memory cells in the memory array detected by the Memory Built-in Self Test circuitry, the first portion of faulty memory cells capable of repair during a repair time. ### Claim 2 (depends on 1) The SDRAM device of claim 1, wherein a repair command is received via a second mode register. ### Claim 3 (depends on 1) The SDRAM device of claim 1, wherein the hard repair capable of completion during the repair time while power is stable. ### Claim 4 (depends on 1) The SDRAM device of claim 1, wherein the status of the test is no errors. ### Claim 5 (depends on 1) The SDRAM device of claim 1, wherein the repair circuitry to perform the hard repair of a second portion of faulty memory cells in the memory array detected by the Memory Built-in Self Test circuitry, the second portion of faulty memory cells capable of repair during the repair time after completion of the hard repair of the first portion of faulty memory cells. ### Claim 6 A system comprising: a dynamic random access memory (DRAM) device, comprising: one or more mode registers, each mode register having a plurality of bits; a memory array; Memory Built-in Self Test circuitry to use patterns to test the memory array, the Memory Built-in Self Test circuitry to store a status of the test of the memory array in a first mode register; and repair circuitry to perform a hard repair of a first portion of faulty memory cells in the memory array detected by the Memory Built-in Self Test circuitry, the first portion of faulty memory cells capable of repair during a repair time, a display communicatively coupled to a processor to display data stored in the DRAM device. ### Claim 7 (depends on 6) The system of claim 6, wherein the DRAM is a Synchronous Dynamic Random Access Memory (SDRAM). ### Claim 8 (depends on 6) The system of claim 6, wherein a repair command is received via a second mode register. ### Claim 9 (depends on 6) The system of claim 6, wherein the hard repair capable of completion during the repair time while power is stable. ### Claim 10 (depends on 6) The system of claim 6, wherein the status of the test is no errors. ### Claim 11 (depends on 6) The system of claim 6, wherein the repair circuitry to perform the hard repair of a second portion of faulty memory cells in the memory array detected by the Memory Built-in Self Test circuitry, the second portion of faulty memory cells capable of repair during the repair time after completion of the hard repair of the first portion of faulty memory cells. ### Claim 12 A method comprising: testing, by Memory Built-in Self Test circuitry in a synchronous dynamic random access memory (SDRAM) device, a memory array in the DRAM using test patterns; storing status of the testing of the memory array in a first mode register of a plurality of mode registers in the SDRAM device, each mode register having a plurality of bits; and performing, by repair circuitry in the SDRAM device, a hard repair of a first portion of faulty memory cells in the memory array detected by the Memory Built-in Self Test circuitry, the first portion of faulty memory cells capable of repair during a repair time. ### Claim 13 (depends on 12) The method of claim 12, wherein a repair command is received via a second mode register. ### Claim 14 (depends on 12) The method of claim 12, wherein the hard repair capable of completion during the repair time while power is stable. ### Claim 15 (depends on 12) The method of claim 12, wherein the status of the testing is no errors. ### Claim 16 (depends on 12) The method of claim 12, wherein the repair circuitry to perform the hard repair of a second portion of faulty memory cells in the memory array detected by the Memory Built-in Self Test circuitry, the second portion of faulty memory cells capable of repair during the repair time after completion of the hard repair of the first portion of faulty memory cells.