# US 12,190,976 B2 · Method and device for checking data, electronic device, and storage medium

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 12,190,976 B2
- Document ID: US12190976B2
- Status: Granted
- Kind: B2
- Application number: 17/854,138
- Filed: 2022-06-30
- Published: 2023-09-28
- Granted: 2025-01-07
- Earliest claimed: 2022-02-08
- Assignees: Changxin Memory Technologies, Inc.
- Applicants: Changxin Memory Technologies, Inc.
- Inventors: Jia Wang
- Web page: https://patentgrep.com/patent/US12190976B2

## CPC

- G11C 29/40: using compression techniques
- G11C 29/42: using error correcting codes [ECC] or parity check
- G06F 11/10: Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G11C 29/1201: {comprising I/O circuitry}
- G11C 29/38: Response verification devices
- G11C 29/4401: {for self repair}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/44: Indication or identification of errors, e.g. for repair
- G11C 2029/0409: {Online test}
- G11C 2029/1202: {Word line control}
- G11C 2029/1204: {Bit line control}
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method, device for checking data, an electronic device and a storage medium are provided. The method includes operations as follows. A memory array is read to obtain read data, and the read data is compressed to obtain first compressed data. The first compressed data is compared with second compressed data, the second compressed data being obtained by compressing written data corresponding to the read data. In responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data is detected, to determine whether the read data is correct. It is determined that the read data is correct if the data of the predetermined bit is consistent with the pre-stored original bit data, otherwise it is determined that the read data is incorrect.

## Claims

### Claim 1

A method for checking data, applied to a memory and comprising:
reading a memory array to obtain read data, and compressing the read data to obtain first compressed data;
comparing the first compressed data with second compressed data, wherein the second compressed data is obtained by compressing written data corresponding to the read data;
detecting, in responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data to determine whether the read data is correct; and
determining, in responsive to that the data of the predetermined bit in the read data is consistent with the pre-stored original bit data, that the read data is correct, and determining, in responsive to that the data of the predetermined bit in the read data is inconsistent with the pre-stored original bit data, that the read data is incorrect, wherein the original bit data is data of the predetermined bit in the written data corresponding to the read data; and, wherein the method further comprises:
compressing the written data to obtain the second compressed data;
extracting the data of the predetermined bit in the written data; and
storing the second compressed data and the data of the predetermined bit in the written data, and writing the written data into the memory array.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
determining, by simulation testing according to sample data, a bit of which an error rate exceeds a predetermined threshold; and
determining the bit of which the error rate exceeds the predetermined threshold as the predetermined bit.

### Claim 3 (depends on 1)

The method of claim 1, wherein the compressing the written data to obtain the second compressed data comprises:
dividing the written data into multiple parts of data according to a data amount of the second compressed data;
performing, for each part of data, compression processing based on an exclusive- or operation on each bit of data in the part of data, to obtain compression results of the multiple parts of data, the compression result comprising 1-bit data; and
obtaining the second compressed data according to the compression results of the multiple parts of data.

### Claim 4 (depends on 3)

The method of claim 3, wherein the performing, for each part of data, the compression processing based on an exclusive- or operation on each bit of data in the part of data to obtain compression results of the multiple parts of data comprises:
dividing each part of data into multiple parts of sub-data, wherein a data amount of each part of sub-data is equal to data amount corresponding to each burst in the memory array;
performing, for each part of sub-data, an exclusive- or operation on each bit of data in the part of sub-data to obtain an intermediate compression result of the sub-data; and
performing, for each part of data, an exclusive- or operation on the intermediate compression results of the multiple parts of sub-data of the part of data, to obtain the compression results of the multiple parts of data.

### Claim 5 (depends on 1)

The method of claim 1, wherein the original bit data is stored in a register.

### Claim 6 (depends on 1)

The method of claim 1, further comprising: after the compressing the read data to obtain first compressed data,
determining that the read data is incorrect in responsive to that the first compressed data is inconsistent with the second compressed data.

### Claim 7 (depends on 1)

A computer-readable storage medium having stored therein computer-executable instructions which, when executed by a processor, are used for implementing the method of claim 1.

### Claim 8

A device for checking data, comprising:
a read-write circuit configured to read a memory array to obtain read data;
a compression circuit configured to compress the read data to obtain first compressed data; and
a checking circuit configured to:
compare the first compressed data with second compressed data, wherein the second compressed data is obtained by compressing written data corresponding to the read data;
detect, in responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data to determine whether the read data is correct; and
determine, in responsive to that the data of the predetermined bit in the read data is consistent with the pre-stored original bit data, that the read data is correct, and determine, in responsive to that the data of the predetermined bit in the read data is inconsistent with the pre-stored original bit data, that the read data is incorrect, wherein the original bit data is data of the predetermined bit in the written data corresponding to the read data;
the compression circuit further configured to compress the written data to obtain the second compressed data,
a selection circuit configured to extract the data of the predetermined bit in the written data; and
the read-write circuit configured to store the second compressed data and the data of the predetermined bit in the written data, and write the written data into the memory array.

### Claim 9 (depends on 8)

The device of claim 8, wherein
the selection circuit is further configured to determine, by simulation testing according to sample data, a bit of which an error rate exceeds a predetermined threshold; and
the selection circuit is further configured to determine the bit of which the error rate exceeds the predetermined threshold as the predetermined bit.

### Claim 10 (depends on 8)

The device of claim 8, wherein the compression circuit is configured to:
divide the written data into multiple parts of data according to a data amount of the second compressed data;
perform, for each part of data, compression processing based on an exclusive- or operation on each bit of data in the part of data, to obtain compression results of the multiple parts of data, the compression result comprising 1-bit data, and
obtain the second compressed data according to the compression results of the multiple parts of data.

### Claim 11 (depends on 10)

The device of claim 10, wherein the compression circuit is further configured to:
divide each part of data into multiple parts of sub-data, wherein a data amount of each part of sub-data is equal to data amount corresponding to each burst in the memory array;
perform, for each part of sub-data, an exclusive- or operation on each bit of data in the part of sub-data to obtain an intermediate compression result of the sub-data; and
perform, for each part of data, an exclusive- or operation on the intermediate compression results of the multiple parts of sub-data of the part of data, to obtain the compression results of the multiple parts of data.

### Claim 12 (depends on 8)

The device of claim 8, wherein the original bit data is stored in a register.

### Claim 13 (depends on 8)

The device of claim 8, wherein
the checking circuit is further configured to, after the compression circuit compresses the read data to obtain the first compressed data, determine that the read data is incorrect in responsive to that the first compressed data is inconsistent with the second compressed data.

### Claim 14

An electronic device, comprising:
a processor; and
a memory in communication connection with the processor,
wherein the memory stores computer-executable instructions; and
the processor executes the computer-executable instructions stored in the memory to implement:
reading a memory array to obtain read data, and compressing the read data to obtain first compressed data;
comparing the first compressed data with second compressed data, wherein the second compressed data is obtained by compressing written data corresponding to the read data;
detecting, in responsive to that the first compressed data is consistent with the second compressed data, whether data of a predetermined bit in the read data is consistent with pre-stored original bit data to determine whether the read data is correct; and
determining, in responsive to that the data of the predetermined bit in the read data is consistent with the pre-stored original bit data, that the read data is correct, and determining, in responsive to that the data of the predetermined bit in the read data is inconsistent with the pre-stored original bit data, that the read data is incorrect, wherein the original bit data is data of the predetermined bit in the written data corresponding to the read data; and,
wherein the processor executes the computer-executable instructions stored in the memory to implement:
compressing the written data to obtain the second compressed data;
extracting the data of the predetermined bit in the written data; and
storing the second compressed data and the data of the predetermined bit in the written data, and writing the written data into the memory array.

### Claim 15 (depends on 14)

The electronic device of claim 14, wherein the processor executes the computer-executable instructions stored in the memory to implement:
determining, by simulation testing according to sample data, a bit of which an error rate exceeds a predetermined threshold; and
determining the bit of which the error rate exceeds the predetermined threshold as the predetermined bit.

### Claim 16 (depends on 14)

The electronic device of claim 14, wherein the processor executes the computer-executable instructions stored in the memory to implement:
dividing the written data into multiple parts of data according to a data amount of the second compressed data;
performing, for each part of data, compression processing based on an exclusive- or operation on each bit of data in the part of data, to obtain compression results of the multiple parts of data, the compression result comprising 1-bit data; and
obtaining the second compressed data according to the compression results of the multiple parts of data.

### Claim 17 (depends on 16)

The electronic device of claim 16, wherein the processor executes the computer-executable instructions stored in the memory to implement:
dividing each part of data into multiple parts of sub-data, wherein a data amount of each part of sub-data is equal to data amount corresponding to each burst in the memory array;
performing, for each part of sub-data, an exclusive- or operation on each bit of data in the part of sub-data to obtain an intermediate compression result of the sub-data; and
performing, for each part of data, an exclusive- or operation on the intermediate compression results of the multiple parts of sub-data of the part of data, to obtain the compression results of the multiple parts of data.