# US 12,190,974 B2 · DRAM retention test method for dynamic error correction

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- Number: US 12,190,974 B2
- Document ID: US12190974B2
- Status: Granted
- Kind: B2
- Application number: 18/138,661
- Filed: 2023-04-24
- Published: 2023-11-23
- Granted: 2025-01-07
- Earliest claimed: 2011-10-24
- Assignees: Rambus Inc.
- Applicants: Rambus Inc.
- Inventors: Ely Tsern; Frederick A Ware; Suresh Rajan; Thomas Vogelsang
- Web page: https://patentgrep.com/patent/US12190974B2

## CPC

- G11C 29/24: Accessing extra cells, e.g. dummy cells or redundant cells
- G06F 11/1008: {in individual solid state devices (G06F11/1004 takes precedence)}
- G11C 29/50016: {of retention}
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 2029/4402: {Internal storage of test result, quality data, chip identification, repair information}
- G11C 2211/4061: Calibration or ate or cycle tuning
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.

## Claims

### Claim 1

An integrated circuit (IC) dynamic random access memory (DRAM) memory controller comprising:
a storage interface to access storage, the storage to store row address information of storage cells that are associated with a detected error;
test circuitry to perform test operations on an array of DRAM storage cells, the array of DRAM storage cells organized into multiple rows that are accessible via corresponding row addresses, each of the multiple rows including multiple columns of DRAM storage cells that are accessible via corresponding column addresses, the test circuitry operable to
perform consecutive access operations to access column data corresponding to each of the multiple columns of each of the multiple rows;
for each of the consecutive access operations, determine whether the accessed column data includes at least one error; and
if at least one error is detected in the accessed column data,
correct the at least one error, and
update the storage to include the corresponding row address of the detected column data that included the at least one error.

### Claim 2 (depends on 1)

The IC DRAM memory controller of claim 1, wherein the test circuitry further comprises:
error circuitry to correct the at least one error using an error correction code.

### Claim 3 (depends on 1)

The IC DRAM memory controller of claim 1, wherein:
the test circuitry performs the test operations during a normal data transfer mode of operation.

### Claim 4 (depends on 1)

The IC DRAM memory controller of claim 1, wherein the test circuitry further comprises:
a test counter to generate consecutive column addresses corresponding to each of the multiple columns of each of the multiple rows.

### Claim 5 (depends on 1)

The IC DRAM memory controller of claim 1, wherein the storage interface further comprises:
sideband pins for coupling to a sideband bus, the sideband bus to interface the IC DRAM memory controller to the storage.

### Claim 6 (depends on 5)

The IC DRAM memory controller of claim 5, wherein the sideband pins are for coupling to a serial bus.

### Claim 7 (depends on 1)

The IC DRAM memory controller of claim 1, wherein:
the stored row address information of the storage cells that are associated with the detected error correspond to storage locations that failed a retention test.

### Claim 8

A method of operation in an integrated circuit (IC) dynamic random access memory (DRAM) memory controller, the method comprising:
performing test operations on an array of DRAM storage cells, the array of DRAM storage cells organized into multiple rows that are accessible via corresponding row addresses, each row address including multiple columns that are accessible via corresponding column addresses, the test operations including
performing consecutive access operations to access column data corresponding to each of the multiple columns of each of the multiple rows;
for each of the consecutive access operations, determining whether the accessed column data includes at least one error; and
if at least one error is detected in the accessed column data,
correcting the at least one error, and
storing the corresponding row address of the detected column data that included the at least one error, the storing carried out with off-chip storage.

### Claim 9 (depends on 8)

The method of claim 8, wherein performing the test operations further comprises:
performing the test operations during a normal data transfer mode of operation.

### Claim 10 (depends on 8)

The method of claim 8, wherein the storing of the corresponding row address of the detected column data that included the at least one error further comprises:
interfacing the IC DRAM memory controller with the off-chip storage via a serial bus.

### Claim 11 (depends on 8)

The method of claim 8, wherein the correcting of the at least one error further comprises:
correcting the at least one error using an error correction code.

### Claim 12 (depends on 8)

The method of claim 8, further comprising:
controlling the test operations with a state machine.

### Claim 13 (depends on 8)

The method of claim 8, further comprising:
during an initialization mode of operation, loading the off-chip storage with prior fail address information, the prior fail address information obtained during prior test operations.

### Claim 14 (depends on 8)

The method of claim 8, wherein the performing consecutive access operations to access column data corresponding to each of the multiple columns of each of the multiple rows further comprises:
generating consecutive column addresses corresponding to each of the multiple columns with a test counter.

### Claim 15

An integrated circuit (IC) dynamic random access memory (DRAM) memory controller comprising:
a storage interface to access storage, the storage to store row address information of storage cells that are associated with a detected error;
test circuitry including
a test counter to generate consecutive column addresses to access corresponding columns of DRAm storage cells;
error detection circuitry, for each generated column address, to determine whether column data stored in the column storage cells corresponding to the column address includes at least one error; and
error correction circuitry, if at least one error is detected, to correct the at least one error, and
circuitry to update the storage to include a corresponding row address of the detected column data that included the at least one error.

### Claim 16 (depends on 15)

The IC DRAM memory controller of claim 15, wherein the storage interface further comprises:
sideband pins for coupling to a sideband bus, the sideband bus to interface the IC DRAM memory controller to the storage.

### Claim 17 (depends on 15)

The IC DRAM memory controller of claim 15, wherein:
the test circuitry performs the test operations during a normal data transfer mode of operation.

### Claim 18 (depends on 15)

The IC DRAM memory controller of claim 15, wherein the test circuitry further comprises:
a state machine to control the test operations.

### Claim 19 (depends on 15)

The IC DRAM memory controller of claim 15, wherein:
during an initialization mode of operation, the storage is loaded with prior fail address information, the prior fail address information obtained during prior test operations.

### Claim 20 (depends on 15)

The IC DRAM memory controller of claim 15, wherein the error correction circuitry employs an error correction code to correct the at least one error.