# US 12,190,968 B2 · Memory circuit, system and method for rapid retrieval of data sets

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- Number: US 12,190,968 B2
- Document ID: US12190968B2
- Status: Granted
- Kind: B2
- Application number: 18/420,073
- Filed: 2024-01-23
- Published: 2024-05-16
- Granted: 2025-01-07
- Earliest claimed: 2015-09-30
- Assignees: Sunrise Memory Corporation
- Applicants: Sunrise Memory Corporation
- Inventors: Eli Harari
- Web page: https://patentgrep.com/patent/US12190968B2

## CPC

- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)}
- G06N 3/063: using electronic means
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5635: {Erasing circuits}
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM}
- G11C 16/0466: {comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/0491: {Virtual ground arrays}
- G11C 16/10: Programming or data input circuits
- H10B 41/10: characterised by the top-view layout
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 1/62: Capacitors having potential barriers
- H10D 30/0413: {of FETs having charge-trapping gate insulators, e.g. MNOS transistors}
- H10D 30/6723: {having light shields}
- H10D 30/693: {Vertical IGFETs having charge trapping gate insulators}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/037: {comprising charge-trapping insulators}
- G11C 16/26: Sensing or reading circuits; Data output circuits
- H10B 43/10: characterised by the top-view layout
- H10D 30/6728: {Vertical TFTs}
- H10D 30/674: {characterised by the active materials}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G06N: COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A 3-dimensional array of NOR memory strings being organized by planes of NOR memory strings, in which (i) the storage transistors in the NOR memory strings situated in a first group of planes are configured to be programmed, erased, program-inhibited or read in parallel, and (ii) the storage transistors in NOR memory strings situated within a second group of planes are configured for storing resource management data relating to data stored in the storage transistors of the NOR memory strings situated within the first group of planes, wherein the storage transistors in NOR memory strings in the second group of planes are configured into sets.

## Claims

### Claim 1

A 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate, wherein each NOR memory string comprises:
a first group of thin-film memory transistors; and
a second group of thin-film memory transistors, wherein the thin-film memory transistors in the first group and the thin-film memory transistors in the second group share a common drain region and a common source region, wherein the thin-film memory transistors in the first group are configured to be accessed within a first access time and the thin-film memory transistors in the second group are configured to be accessed within a second access time, and wherein the first access time is less than the second access time.

### Claim 2 (depends on 1)

The 3-dimensional array of claim 1, wherein memory operation support circuitry is provided at the planar surface of the semiconductor substrate.

### Claim 3 (depends on 1)

The 3-dimensional array of claim 1, wherein the memory operation support circuit comprises a plurality of sense amplifiers each configured to be selectively coupled to either a common drain region or a common source region of the thin-film memory transistors in one of the NOR memory strings of the array, and wherein the first group of thin-film transistors of that NOR memory string are each closer in proximity to the coupled sense amplifier than any of the second group of the thin-film transistors in that memory string.

### Claim 4 (depends on 3)

The 3-dimensional array of claim 3, wherein the planar surface of the semiconductor substrate is divided into a plurality of non-overlapping blocks, and wherein the sense amplifiers located in each block are coupled to the common drain regions or the common source regions of NOR memory strings, the coupled common drain regions or the coupled common source regions each being within a predetermined distance from that block along a direction substantially parallel to the planar surface of the semiconductor substrate.

### Claim 5 (depends on 4)

The 3-dimensional array of claim 4 wherein, within each block, one or more types of circuits are provided for programming, erase, program-inhibit or read operations of the NOR memory strings whose common drain regions or common source regions are coupled to the sense amplifiers within the block.

### Claim 6 (depends on 5)

The 3-dimensional array of claim 5, wherein the types of circuits comprise one or more of: voltage source, data registers, XOR gates and input/output (I/O) terminals.

### Claim 7 (depends on 1)

The 3-dimensional array of claim 1, wherein data stored in the thin-film memory transistors of the first groups in the NOR memory strings of the array comprise values of operational parameters to be used in accessing the thin-film memory transistors in the second groups of the NOR memory strings of the array.

### Claim 8 (depends on 7)

The 3-dimensional array of claim 7, wherein the values of operational parameters include information regarding the files or data sets stored in the second groups of thin-film memory transistors in the NOR memory strings of the array.

### Claim 9 (depends on 8)

The 3-dimensional array of claim 8, wherein accesses to the thin-film transistors in the NOR memory array are controlled by a system controller, and wherein the information regarding the files or data sets include, for each file or data set, a unique identifier number assigned by the system controller, together with an index number that identifies the type pertaining to the file or data set.

### Claim 10 (depends on 8)

The 3-dimensional array of claim 8, wherein (i) the first groups of thin-film transistors in the NOR memory strings of the array are organized into one or more blocks, (ii) the array further comprises, associated with each block, a comparison circuit, (iii) during each memory access, the system controller broadcasts a selected unique identifier number, and (iv) the comparison circuit of each block matches the selected unique identifier number against the unique identifier number stored within the first groups of thin-film transistors associated with the block.

### Claim 11 (depends on 8)

The 3-dimensional array of claim 8, wherein the information regarding the files or data sets comprises resource management data.

### Claim 12 (depends on 11)

The array of claim 11, wherein the resource management data relates to a group of the files or data sets, and wherein, with respect to each file or data set within the group, the resource management data comprises one or more of: a number of accesses to the file or data set, an indication of erase eligibility for the file or data set, an indication of defective data in the file or data set, and a time stamp associated with the file or data set.

### Claim 13 (depends on 11)

The 3-dimensional array of claim 11, wherein the resource management data comprises one or more of: file management data, configuration parameter values, mapping of addresses of defective files or data sets to addresses of their replacement files or data sets, data identifiers, look-up tables, link-lists, timestamps, error detection and error correction data, optimum voltages and pulse shapes and durations for erase, program, program-inhibit, program scrub, read, margin read, read refresh, read scrub operations, error correcting codes, data recovery modes, and other system parameters.

### Claim 14 (depends on 1)

The 3-dimensional array of claim 1, wherein thin-film memory transistors of one or more of the first groups in the NOR memory strings of array are configured to be programmed or erased simultaneously.

### Claim 15 (depends on 1)

The 3-dimensional array of claim 1, wherein thin-film memory transistors of one or more of the first groups in the NOR memory strings of array are configured to be programmed or erased simultaneously.

### Claim 16 (depends on 1)

The 3-dimensional array of claim 1, wherein the thin-film memory transistors in each NOR memory strings are organized in pairs, with each pair of thin-film memory transistors being configured to store a bit value and its complement.

### Claim 17 (depends on 1)

The 3-dimensional arrays of claim 1, wherein selected ones of the NOR memory strings are provided as reference NOR memory strings for use in conjunction with reading thin-film memory transistors of other NOR memory strings in the array.

### Claim 18 (depends on 17)

The 3-dimensional array of claim 17, wherein thin-film transistors of each group in each reference NOR memory string are used in conjunction with reading of thin-film memory transistors of the corresponding group of the NOR memory string being read.

### Claim 19 (depends on 1)

The 3-dimensional array of claim 1, further comprising a plurality of conductors each serving as a gate electrode common to a plurality of thin-film memory transistors in the NOR memory strings of the 3-dimensional array.