# US 12,190,967 B2 · Voltage generation circuit and semiconductor memory device

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- Number: US 12,190,967 B2
- Document ID: US12190967B2
- Status: Granted
- Kind: B2
- Application number: 17/901,512
- Filed: 2022-09-01
- Published: 2023-09-28
- Granted: 2025-01-07
- Earliest claimed: 2022-03-23
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Takumi Fujimoto
- Web page: https://patentgrep.com/patent/US12190967B2

## CPC

- G11C 16/30: Power supply circuits
- H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps}
- G11C 5/145: {Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence)}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/32: Timing circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A voltage generation circuit includes a plurality of charge pumps connected to a first node, and a control circuit that controls the number of active charge pumps among the plurality of charge pumps based on a period in which a voltage of the first node satisfies a condition.

## Claims

### Claim 1

A voltage generation circuit comprising:
a plurality of charge pumps each connected to a first node;
a control circuit configured to control a number of active charge pumps among the plurality of charge pumps based on a period in which a voltage of the first node satisfies a predetermined condition; and
wherein the control circuit is configured to reduce the number of active charge pumps based on a first period in which the voltage of the first node is at least a first voltage in a state where at least two charge pumps among the plurality of charge pumps are active.

### Claim 2 (depends on 1)

The voltage generation circuit according to claim 1, wherein the control circuit is configured to increase a number of inactive charge pumps among the plurality of charge pumps based on a second period in which the voltage of the first node is maintained to be less than the first voltage in a state where at least one charge pump among the plurality of charge pumps is inactive.

### Claim 3 (depends on 2)

The voltage generation circuit according to claim 2, wherein the first period and the second period are periods based on a clock signal.

### Claim 4 (depends on 2)

The voltage generation circuit according to claim 2, wherein the control circuit is configured to control all of the plurality of charge pumps to be active charge pumps when the voltage of the first node is less than a second voltage, the second voltage being less than the first voltage.

### Claim 5 (depends on 4)

The voltage generation circuit according to claim 4, further comprising:
a first resistor having a first terminal and a second terminal, the first terminal connected to the first node, the second terminal connected to a second node;
a second resistor having a first terminal connected to the second node; and
a first operational amplifier having a first terminal and a second terminal, the first terminal connected to the second node, the second terminal having a third voltage applied thereto, the first operational amplifier configured to output a first comparison result of a voltage of the second node and the third voltage to the control circuit,
wherein the first period and the second period are periods based on the first comparison result.

### Claim 6 (depends on 5)

The voltage generation circuit according to claim 5, wherein the third voltage is the voltage of the second node when the voltage of the first node is equal to the first voltage.

### Claim 7 (depends on 5)

The voltage generation circuit according to claim 5, further comprising:
a third resistor arranged to connect the first node to the first resistor in series, the third resistor having a first terminal connected to the first node and a second terminal connected to the third node together with the first terminal of the first resistor; and
a second operational amplifier having a first terminal and a second terminal, the first terminal connected to the third node and the second terminal, the second terminal having a fourth voltage applied thereto, the second operational amplifier configured to output a second comparison result of a voltage of the third node and the fourth voltage to the control circuit,
wherein the voltage generation circuit is configured to determine whether the voltage of the first node is less than the second voltage based on the second comparison result.

### Claim 8 (depends on 7)

The voltage generation circuit according to claim 7, wherein the fourth voltage is the voltage of the third node when the voltage of the third node is equal to the second voltage.

### Claim 9 (depends on 8)

The voltage generation circuit according to claim 8, wherein the third voltage is equal to the fourth voltage.

### Claim 10 (depends on 1)

The voltage generation circuit according to claim 1, wherein, when the voltage of the first node is less than the first voltage, the control circuit starts to generate a voltage by using the active charge pumps among the plurality of charge pumps.

### Claim 11 (depends on 10)

The voltage generation circuit according to claim 10, wherein the control circuit is configured to generate a voltage by using the active charge pumps among the plurality of charge pumps during a third period, and to stop the generation of the voltage by using the active charge pumps among the plurality of charge pumps during a fourth period after the third period ends.

### Claim 12 (depends on 1)

A semiconductor memory device comprising:
the voltage generation circuit according to claim 1; and
a memory cell,
wherein the semiconductor memory device is configured to supply the voltage of the first node to the memory cell.

### Claim 13 (depends on 12)

The semiconductor memory device according to claim 12,
wherein: when the voltage of the first node is less than the first voltage, the control circuit causes boost operations of the active charge pumps among the plurality of charge pumps to be started.

### Claim 14 (depends on 13)

The semiconductor memory device according to claim 13, wherein the control circuit is configured to generate a voltage by using the active charge pumps among the plurality of charge pumps during the first period, and stop the generation of the voltage using the active charge pumps among the plurality of charge pumps during a second period after the first period ends.
