# US 12,190,966 B2 · Memory system and processing method of memory system

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- Number: US 12,190,966 B2
- Document ID: US12190966B2
- Status: Granted
- Kind: B2
- Application number: 17/899,447
- Filed: 2022-08-30
- Published: 2023-09-07
- Granted: 2025-01-07
- Earliest claimed: 2022-03-01
- Assignees: Kioxia Corporation
- Applicants: Kioxia Corporation
- Inventors: Tomoya Sanuki; Hitomi Tanaka; Tatsuro Hitomi; Yasuhito Yoshimizu; Masayuki Miura; Yoshihiro Ohba
- Web page: https://patentgrep.com/patent/US12190966B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/34: Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/00: EEPROM devices comprising charge-trapping gate insulators
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector is provided. The method includes detaching the semiconductor memory chip from the connector, performing an annealing process with respect to the semiconductor memory chip detached from the connector, and after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

## Claims

### Claim 1

A method of processing a memory system that includes a substrate with a connector and a semiconductor memory chip connected to the connector, the method comprising:
detaching the semiconductor memory chip from the connector;
performing an annealing process with respect to the semiconductor memory chip detached from the connector; and
after the annealing process, attaching the semiconductor memory chip to the connector on the substrate.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising:
reading first information related to the annealing process from the semiconductor memory chip before the annealing process; and
after the annealing process, updating the first information and writing the updated first information into the semiconductor memory chip.

### Claim 3 (depends on 2)

The method according to claim 2, wherein
the first information is read from a predetermined region of the semiconductor memory chip, and
the updated first information is written into the predetermined region of the semiconductor memory chip.

### Claim 4 (depends on 2)

The method according to claim 2, wherein the first information includes a number of times the annealing process has been performed with respect to the semiconductor memory chip.

### Claim 5 (depends on 1)

The method according to claim 1, further comprising:
reading second information indicating operation voltages of the semiconductor memory chip from the semiconductor memory chip before the annealing process; and
after the annealing process, updating the second information and writing the updated second information into the semiconductor memory chip.

### Claim 6 (depends on 5)

The method according to claim 5, wherein
the second information is read from a predetermined region of the semiconductor memory chip, and
the updated second information is written into the predetermined region of the semiconductor memory chip.

### Claim 7 (depends on 5)

The method according to claim 5, wherein
the operation voltages read before the annealing process indicate a plurality of voltages used for storing data of a first number of bits in a memory cell of the semiconductor memory chip, and
the operation voltages in the updated second information indicates one or more voltages used for storing data of a second number of bits in the memory cell, the second number of bits being less than the first number of bits.

### Claim 8 (depends on 1)

The method according to claim 1, further comprising:
reading user data from the semiconductor memory chip before the annealing process; and
after the annealing process, writing the user data into the semiconductor memory chip.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the annealing process is performed at a temperature in a range that is 125° C. or higher and 250° C. or lower and for a duration of a range that is 1 hour or longer and 3 days or shorter.

### Claim 10 (depends on 1)

The method according to claim 1, wherein a width of a threshold voltage distribution, which corresponds to a certain bit value, of memory cells of the semiconductor memory chip after the annealing process is narrower than a width of the threshold voltage distribution of the memory cells before the annealing process.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the semiconductor memory chip is a NAND flash memory.

### Claim 12 (depends on 1)

The method according to claim 1, wherein the semiconductor memory chip has a ball grid array (BGA) structure that is connected to the connector on the substrate.