# US 12,190,965 B2 · Coding to decrease error rate discrepancy between pages

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- Number: US 12,190,965 B2
- Document ID: US12190965B2
- Status: Granted
- Kind: B2
- Application number: 17/894,398
- Filed: 2022-08-24
- Published: 2024-02-29
- Granted: 2025-01-07
- Earliest claimed: 2022-08-24
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Curtis Egan
- Web page: https://patentgrep.com/patent/US12190965B2

## CPC

- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 29/06: Acceleration testing
- G11C 29/4401: {for self repair}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 2029/5002: {Characteristic}
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Methods, systems, and devices for coding to decrease error rate discrepancy between pages are described. For example, to identify a unit-distance code for operating a memory device, voltage drifts of a set of read voltages after a duration may be identified and each of the read voltages may be mapped to one of a set of pages of the memory cell using various possible unit-distance codes. Thus, for each unit-distance code the set of pages may be associated with respective subsets of the set of read voltages. Then, for each unit-distance code a set of average read voltage drifts corresponding to one of the set of pages may be identified. The memory device may be operated using a unit-distance code associated with a smaller range of the set of average read voltage drifts than ranges of sets of average read voltage drifts associated with other unit-distance codes.

## Claims

### Claim 1

A method, comprising:
identifying, after a duration, voltage drifts of a plurality of read voltages, the plurality of read voltages corresponding to a plurality of voltage levels between adjacent voltage threshold regions of a memory cell at a memory device;
mapping the plurality of read voltages to one of a plurality of pages of the memory cell using a unit-distance code, wherein the plurality of pages are associated with respective subsets of the plurality of read voltages according to the unit-distance code;
identifying a plurality of average read voltage drifts each corresponding to one of the plurality of pages based at least in part on the voltage drifts of read voltages within the respective subsets of the plurality of read voltages; and
operating the memory device using the unit-distance code based at least in part on a range of the plurality of average read voltage drifts each corresponding to one of the plurality of pages associated with the unit-distance code being less than one or more other ranges of a plurality of average read voltage drifts that each correspond to one of the plurality of pages associated with one or more other unit-distance codes.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
mapping the plurality of read voltages to one of the plurality of pages of the memory cell using a second unit-distance code different than the unit-distance code, wherein the plurality of pages are associated with respective second subsets of the plurality of read voltages according to the second unit-distance code;
identifying a plurality of second average read voltage drifts each corresponding to one of the plurality of pages based at least in part on the voltage drifts of each read voltage within the respective second subsets of the plurality of read voltages; and
selecting to operate the memory device using the unit-distance code based at least in part on a second range of the plurality of second average read voltage drifts being greater than range of the plurality of average read voltage drifts, wherein operating the memory device is based at least in part on the selecting.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
comparing the second range of the plurality of second average read voltage drifts to the range of the plurality of average read voltage drifts, wherein mapping the plurality of read voltages to one of the plurality of pages of the memory cell using the unit-distance code is based at least in part on the second range of the plurality of second average read voltage drifts exceeding the range of the plurality of average read voltage drifts.

### Claim 4 (depends on 1)

The method of claim 1, further comprising:
performing summation operations on the voltage drifts of the read voltages within the respective subsets of the plurality of read voltages to identify composite voltage drifts each corresponding to one of the plurality of pages, wherein identifying the plurality of average read voltage drifts is based at least in part on performing the summation operations.

### Claim 5 (depends on 4)

The method of claim 4, wherein identifying the plurality of average read voltage drifts further comprises:
dividing each of the composite voltage drifts by a quantity of the read voltages in the respective subsets of the plurality of read voltages.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
programming a plurality of memory cells at the memory device; and
increasing a temperature of the memory device for the duration, wherein identifying the voltage drifts of the plurality of read voltages is based at least in part on increasing the temperature of the memory device for the duration.

### Claim 7 (depends on 1)

The method of claim 1, wherein:
the memory cell is a quad-level cell (QLC) and comprises sixteen voltage threshold regions; and
mapping the plurality of read voltages to one of the plurality of pages comprises mapping fifteen read voltages to one of four pages of the memory cell.

### Claim 8 (depends on 1)

The method of claim 1, wherein:
the memory cell is a tri-level cell (TLC) or a multi-level cell (MLC) and comprises eight voltage threshold regions or more than sixteen voltage threshold regions; and
mapping the plurality of read voltages to one of the plurality of pages comprises mapping seven read voltages to one of three pages of the memory cell or mapping more than fifteen read voltages to more than four pages of the memory cell.

### Claim 9 (depends on 1)

The method of claim 1, wherein the memory cell comprises a floating gate configuration or a replacement gate configuration.

### Claim 10 (depends on 1)

The method of claim 1, wherein the unit-distance code comprises a Gray code.

### Claim 11

A method, comprising:
operating a memory device using a first unit-distance code that indicates a mapping between a plurality of pages of a memory cell and respective first subsets of a plurality of read voltages;
receiving a read command to retrieve data from the memory cell, the data associated with a first page from the plurality of pages;
selecting, from the plurality of read voltages, a second subset of the plurality of read voltages that are associated with the first page according to a second unit-distance code, wherein the second unit-distance code indicates a mapping between the plurality of pages of the memory cell and respective second subsets of the plurality of read voltages; and
retrieving, from the memory cell, the data indicated by the read command based at least in part on applying one or more of the second subset of the plurality of read voltages to the memory cell, wherein a range of average read voltage drifts that each correspond to one of the plurality of pages and is based at least in part on voltage drifts of the read voltages within respective first subsets of the plurality of read voltages indicated by the first unit-distance code is greater than a range of average read voltage drifts that each correspond to one of the plurality of pages and is based at least in part on voltage drifts of the read voltages within respective second subsets of the plurality of read voltages indicated by the second unit-distance code.

### Claim 12 (depends on 11)

The method of claim 11, wherein:
the plurality of read voltages are each associated with a voltage drift after a duration.

### Claim 13 (depends on 11)

The method of claim 11, further comprising:
receiving second data for storage in the memory cell;
mapping the second data to a voltage threshold region of the memory cell using the second unit-distance code; and
writing the data to the plurality of pages in the memory cell based at least in part on mapping the data to the voltage threshold region using the second unit-distance code.

### Claim 14 (depends on 11)

The method of claim 11, wherein for the first unit-distance code and the second unit-distance code, a one-bit change occurs in data stored by only one of the plurality of pages between a representation of data stored by adjacent voltage threshold regions of the memory cell.

### Claim 15 (depends on 11)

The method of claim 11, wherein:
the memory cell is a quad-level cell (QLC) and comprises four pages; and
selecting the second subset of the plurality of read voltages comprises selecting three read voltages or four read voltages from fifteen read voltages according to the second unit-distance code.

### Claim 16 (depends on 11)

The method of claim 11, wherein:
the memory cell is a tri-level cell (TLC) or a multi-level cell (MLC) and comprises three pages or more than four pages; and
selecting the second subset of the plurality of read voltages comprises selecting two read voltages, three read voltages, or more than four read voltages from eight read voltages or more than fifteen read voltages according to the second unit-distance code.

### Claim 17 (depends on 11)

The method of claim 11, wherein the memory cell comprises a floating gate configuration or a replacement gate configuration.

### Claim 18 (depends on 11)

The method of claim 11, wherein the first unit-distance code and the second unit-distance code comprise a Gray code.

### Claim 19

A memory system, comprising:
one or more memory devices comprising a plurality of memory cells, the plurality of memory cells each comprising a plurality of pages; and
processing circuitry coupled with the one or more memory devices and configured to cause the memory system to:
operate the one or more memory devices using a first unit-distance code that indicates a mapping between the plurality of pages of a memory cell of the plurality of memory cells and respective first subsets of a plurality of read voltages;
receive a read command to retrieve data from the memory cell of the plurality of memory cells, the data associated with a first page from the plurality of pages;
select, from the plurality of read voltages, a second subset of the plurality of read voltages that are associated with the first page according to a second unit-distance code, wherein the second unit-distance code indicates a mapping between the plurality of pages of the memory cell and respective second subsets of the plurality of read voltages; and
retrieve, from the memory cell, the data indicated by the read command based at least in part on applying one or more of the second subset of the plurality of read voltages to the memory cell, wherein a range of average read voltage drifts that each correspond to one of the plurality of pages and is based at least in part on voltage drifts of the read voltages within respective first subsets of the plurality of read voltages indicated by the first unit-distance code is greater than a range of average read voltage drifts that each correspond to one of the plurality of pages and is based at least in part on voltage drifts of the read voltages within respective second subsets of the plurality of read voltages indicated by the second unit-distance code.

### Claim 20 (depends on 19)

The memory system of claim 19, wherein:
the plurality of read voltages are each associated with a voltage drift after a duration.

### Claim 21 (depends on 19)

The memory system of claim 19, wherein the processing circuitry is further configured to cause the memory system to:
receive second data for storage in the memory cell;
map the second data to a voltage threshold region of the memory cell using the second unit-distance code; and
write the data to the plurality of pages in the memory cell based at least in part on mapping the data to the voltage threshold region using the second unit-distance code.

### Claim 22 (depends on 19)

The memory system of claim 19, wherein for the first unit-distance code and the second unit-distance code, a one-bit change occurs in data stored by only one of the plurality of pages between a representation of data stored by adjacent voltage threshold regions of the memory cell.

### Claim 23 (depends on 19)

The memory system of claim 19, wherein:
the memory cell is a quad-level cell (QLC) and comprises four pages; and
selecting the second subset of the plurality of read voltages comprises selecting three read voltages or four read voltages from fifteen read voltages according to the second unit-distance code.

### Claim 24 (depends on 19)

The memory system of claim 19, wherein:
the memory cell is a tri-level cell (TLC) or a multi-level cell (MLC) and comprises three pages or more than four pages; and
selecting the second subset of the plurality of read voltages comprises selecting two read voltages, three read voltages, or more than four read voltages from eight read voltages or more than fifteen read voltages according to the second unit-distance code.

### Claim 25 (depends on 19)

The memory system of claim 19, wherein the memory cell comprises a floating gate configuration or a replacement gate configuration.