# US 12,190,963 B2 · Methods of operating memory devices based on sub-block positions and related memory system

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- Number: US 12,190,963 B2
- Document ID: US12190963B2
- Status: Granted
- Kind: B2
- Application number: 18/235,838
- Filed: 2023-08-19
- Published: 2023-12-07
- Granted: 2025-01-07
- Earliest claimed: 2017-09-05
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Se-Hwan Park; Wan-Dong Kim
- Web page: https://patentgrep.com/patent/US12190963B2

## CPC

- G11C 16/24: Bit-line control circuits
- G06F 13/1668: {Details of memory controller}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 16/08: Address circuits; Decoders; Word-line control circuits
- G11C 16/10: Programming or data input circuits
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G06F 2213/0024: Peripheral component interconnect [PCI]
- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/32: Timing circuits
- G11C 2211/5648: Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/40: characterised by the peripheral circuit region
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

A memory device may include a memory block operatively connected to a common source line and a plurality of bit lines, wherein the memory block may include first and second sub-blocks each having a respective position in the memory block relative to the common source line and the plurality of bit lines. The memory device mat be operated by receiving a command and an address from outside the memory device and performing a precharge operation on the memory block in response to the command, using a first precharge path through the memory block or a second precharge path through the memory block based on the respective position of the first or second sub-block that includes a word line that is configured to activate responsive to the address.

## Claims

### Claim 1

A memory device comprising:
a plurality of three-dimensional structures including a first structure and a second structure, each of the plurality of three-dimensional structures including:
a plurality of NAND strings that include a first NAND string and a second NAND string, each of the plurality of NAND strings including:
a plurality of memory cells that include a plurality of first memory cells and a plurality of second memory cells, and
a plurality of sub-blocks that include a first sub-block and a second sub-block;
a first channel disposed in the first sub-block;
a second channel disposed in the second sub-block; and
a control logic configured to program the plurality of first memory cells on the first NAND string in a first sub-block of the first structure in a first order, and to program the plurality of second memory cells on the second NAND string in a second sub-block of the second structure in a second order that is different from the first order, wherein:
the plurality of first memory cells of each of the plurality of NAND strings are disposed in the first sub-block of each of the plurality of three-dimensional structures,
the first sub-block of the first structure is disposed at the same vertical level as a first sub-block of the second structure,
a horizontal width of an upper portion of the first channel is greater than a horizontal width of a lower portion of the first channel,
a horizontal width of an upper portion of the second channel is greater than a horizontal width of a lower portion of the second channel,
the first channel and the second channel are connected to each other and configured to form one channel of each of the plurality of NAND strings,
the upper portion of the second channel is connected to the lower portion of the first channel at a particular vertical level, and
at the particular vertical level, the horizontal width of the upper portion of the second channel is greater than the horizontal width of the lower portion of the first channel.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein each of the plurality of memory cells is a non-volatile memory cell.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein each of the plurality of NAND strings includes a string select transistor and a ground select transistor.

### Claim 4 (depends on 3)

The memory device of claim 3, wherein the first sub-block is disposed on the second sub-block, and includes a top end connected to the string select transistor, and
wherein the second sub-block includes a bottom end connected to the ground select transistor.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein the first sub-block of the first structure is disposed at a different vertical level from a second sub-block of the first structure.

### Claim 6 (depends on 1)

The memory device of claim 1, wherein:
the first sub-block is disposed on the second sub-block,
the first order is based on a first direction which extends from a ground select line toward a string select line, and
the second order is based on a second direction which extends from the string select line toward the ground select line.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein:
the first sub-block is disposed on the second sub-block,
the first order is a first sequential order from a bottom end to a top end of the first sub-block of the first structure, and
the second order is a second sequential order from a top end to a bottom end of the second sub-block of the second structure.

### Claim 8 (depends on 7)

The memory device of claim 7, wherein the second sequential order is a reverse of the first sequential order.

### Claim 9 (depends on 1)

The memory device of claim 1, wherein the control logic is configured to program a plurality of third memory cells on a third NAND string of the plurality of NAND strings in a first sub-block of a third structure of the plurality of three-dimensional structures in the first order.

### Claim 10 (depends on 9)

The memory device of claim 9, wherein the control logic is configured to erase the plurality of third memory cells after the control logic programs the plurality of third memory cells.

### Claim 11

A non-volatile memory device comprising:
a three-dimensional structure including a plurality of non-volatile memory cells, and a first sub-block and a second sub-block;
a plurality of word lines connected to the plurality of non-volatile memory cells, and including a first set of word lines disposed in the first sub-block and a second set of word lines disposed in the second sub-block;
a first channel disposed in the first sub-block;
a second channel disposed in the second sub-block; and
a control logic connected to the plurality of word lines, and the control logic configured to:
program non-volatile memory cells connected to the first set of word lines in a first sequential order from a first end to a second end of the first sub-block, and
perform an erase operation on the first sub-block,
wherein a horizontal width of an upper portion of the first channel is greater than a horizontal width of a lower portion of the first channel,
wherein a horizontal width of an upper portion of the second channel is greater than a horizontal width of a lower portion of the second channel,
the first channel and the second channel are connected to each other and configured to form one channel,
the upper portion of the second channel is connected to the lower portion of the first channel at a particular vertical level, and
at the particular vertical level, the horizontal width of the upper portion of the second channel is greater than the horizontal width of the lower portion of the first channel.

### Claim 12 (depends on 11)

The non-volatile memory device of claim 11, wherein the control logic is configured to program non-volatile memory cells connected to the second set of word lines in a second sequential order from a second end to a first end of the second sub-block, and
wherein the second sequential order is different from the first sequential order.

### Claim 13 (depends on 11)

The non-volatile memory device of claim 11, wherein the three-dimensional structure includes a plurality of NAND strings, and
wherein each of the plurality of NAND strings includes a plurality of non-volatile memory cells.

### Claim 14 (depends on 13)

The non-volatile memory device of claim 13, wherein each of the plurality of NAND strings includes a string select transistor and a ground select transistor.

### Claim 15 (depends on 11)

The non-volatile memory device of claim 11, wherein each of the first sub-block and the second sub-block is a unit for performing the erase operation.

### Claim 16

A non-volatile memory device comprising:
a plurality of non-volatile memory cells;
a plurality of word lines connected to the plurality of non-volatile memory cells, and including a first set of word lines and a second set of word lines;
a first channel coupled with the first set of word lines;
a second channel coupled with the second set of word lines; and
a control logic connected to the plurality of word lines and the plurality of non-volatile memory cells, and configured to program the first set of word lines in a first sequential order, and to program the second set of word lines in a second sequential order that is a reverse of the first sequential order,
wherein a horizontal width of an upper portion of the first channel is greater than a horizontal width of a lower portion of the first channel,
wherein a horizontal width of an upper portion of the second channel is greater than a horizontal width of a lower portion of the second channel,
the first channel and the second channel are connected to each other and configured to form one channel,
the upper portion of the second channel is connected to the lower portion of the first channel at a particular vertical level, and
at the particular vertical level, the horizontal width of the upper portion of the second channel is greater than the horizontal width of the lower portion of the first channel.

### Claim 17 (depends on 16)

The non-volatile memory device of claim 16, further comprising:
a first three-dimensional structure in which the first set of word lines are disposed; and
a second three-dimensional structure in which the second set of word lines are disposed,
wherein the first set of word lines and the second set of word lines are disposed in a different vertical level of the respective first and second three-dimensional structures.

### Claim 18 (depends on 17)

The non-volatile memory device of claim 17, wherein each of the first three-dimensional structure and the second three-dimensional structure includes a first sub-block and a second sub-block, and
wherein the first set of word lines are disposed in the first sub-block and the second set of word lines are disposed in the second sub-block.

### Claim 19 (depends on 18)

The non-volatile memory device of claim 18, wherein the control logic is configured to perform an erase operation on the first sub-block.

### Claim 20 (depends on 18)

The non-volatile memory device of claim 18, wherein each of the first sub-block and the second sub-block is a unit for performing an erase operation.