# US 12,190,958 B2 · Storage controller and storage device including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,958 B2 - Document ID: US12190958B2 - Status: Granted - Kind: B2 - Application number: 17/956,225 - Filed: 2022-09-29 - Published: 2023-05-25 - Granted: 2025-01-07 - Earliest claimed: 2021-11-22 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jun-Ho Seo; Sang Yong Yoon; Min Soo Kim; Jeong Hoon Nam; Hyeon Su Bak - Web page: https://patentgrep.com/patent/US12190958B2 ## CPC - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 11/5635: {Erasing circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/16: for erasing blocks, e.g. arrays, words, groups - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A storage device and an operating method of the storage device are provided. The storage device comprises a first non-volatile memory device, a second non-volatile memory device, a third non-volatile memory device a storage controller configured to control the first non-volatile memory device, the second non-volatile memory device, and the third non-volatile memory device, control the first non-volatile memory device to extract a first on-cell count value after a first soft erase operation, set first to third read level offsets of the respective first to third non-volatile memory devices based on the respective first to third on-cell count values, select the first to third defense code parameter sets each corresponding to the respective first to third read level offsets, and transmits first to third read commands based on the selected respective first to third defense code parameter sets to the respective first to third non-volatile memory devices. ## Claims ### Claim 1 A storage device comprising: a first non-volatile memory device; a second non-volatile memory device; a third non-volatile memory device; and a storage controller including processing circuitry configured to set first to third read level offsets of the respective first to third non-volatile memory devices by, extracting a respective one of first through third on-cell count values by performing a respective one of first through third soft erase operations on the respective one of the first to third non-volatile memory devices, and determining a respective one of the first to third read level offsets based on a distribution of the respective one of the first through third on-cell count values determined through the respective one of the first through third soft erase operations, select first to third defense code parameter sets each corresponding to the respective first to third read level offsets, and transmit first to third read commands to the respective first to third non-volatile memory devices based on the selected respective first to third defense code parameter sets such that the first to third read commands include the respective one of the first to third read level offsets. ### Claim 2 (depends on 1) The storage device of claim 1, wherein each of the first to third soft erase operations has a first operation voltage which is lower than a second operation voltage of a normal erase operation. ### Claim 3 (depends on 2) The storage device of claim 2, wherein, in the first soft erase operation, a word line level and an erase time are same for each word line of the first non-volatile memory device. ### Claim 4 (depends on 1) The storage device of claim 1, wherein the storage device is implemented on, a first chip, the first non-volatile memory device and the second non-volatile memory device being on the first chip and a second chip, the third non-volatile memory device being on the second chip, wherein the third read level offset of the third non-volatile memory device is different from the first and second read level offsets of the first non-volatile memory device and the second non-volatile memory device. ### Claim 5 (depends on 1) The storage device of claim 1, wherein a read level offset of a first word line of the first non-volatile memory device is different from a read level offset of a second word line of the first non-volatile memory device. ### Claim 6 (depends on 1) The storage device of claim 1, wherein the storage controller is configured to perform hard decision decoding when the first non-volatile memory device fails in data read, extract the first on-cell count value through the first soft erase operation when the data read fails by the hard decision decoding, adjust a first read level with the first read level offset set by the first on-cell count value, and perform a first read-retry operation. ### Claim 7 (depends on 6) The storage device of claim 6, wherein the storage controller is configured to store environment information of the first non-volatile memory device in response to the data read passing by the first read-retry operation. ### Claim 8 (depends on 1) The storage device of claim 1, wherein the storage controller is configured to perform soft decision decoding in response to data read failing by a read-retry operation based on any one of the first to third read commands, and determine an uncorrectable error when the soft decision decoding fails. ### Claim 9 (depends on 1) The storage device of claim 1, wherein a read level offset of a first temperature region in the first non-volatile memory device is different from a read level offset of a second temperature region in the first non-volatile memory device. ### Claim 10 (depends on 1) The storage device of claim 1, wherein the first non-volatile memory device is configured to, receive a first soft erase command from the storage controller, and perform the first soft erase operation in response to the first soft erase command. ### Claim 11 (depends on 1) The storage device of claim 1, wherein the storage controller is configured to extract the respective one of first through third on-cell count values by, performing a normal read operation on a respective one of the first through third non-volatile memory devices, in response to a host read command from a host device, verifying whether the normal read operation on the respective one of the first through third non-volatile memory devices passes or fails using hard decision (HD) decoding, and extracting a respective one of the first or second on-cell count values by performing soft decision (SD) decoding on the respective one of the first or second non-volatile memory devices that fail the normal read operation. ### Claim 12 A storage device comprising: a first non-volatile memory device having first health index information, the first health index information includes a first on-cell count value extracted from a reference voltage after performing a first soft erase operation on the first non-volatile memory device; a second non-volatile memory device having second health index information, the second health index information includes a second on-cell count value extracted from a reference voltage after performing a second soft erase operation on the second non-volatile memory device; and a storage controller including processing circuitry configured to: generate and store the first and second health index information by, storing the respective one of the first or second on-cell count values as the first health index information stored in the first non-volatile memory device and the second health index information stored in the second non-volatile memory device, respectively, read first data of the first non-volatile memory device by, determining a first read level offset based on a distribution of the first on-cell count values in the first health index information, selecting a first defense code parameter set based on the first read level offset, and transmitting a first read command to the first non-volatile memory device based on the first defense code parameter set such that the first read command include the first read level offset, and read second data of the second non-volatile memory device by, determining a second read level offset based on a distribution of the second on-cell count values in the second health index information, selecting a second defense code parameter set based on the second read level offset, and transmitting a second read command to the second non-volatile memory device based on the second defense code parameter set such that the second read command include the second read level offset, wherein the first read level offset of the first non-volatile memory device is different from the second read level offset of the second non-volatile memory device. ### Claim 13 (depends on 12) The storage device of claim 12, wherein the each of the first and second health index information includes at least one of retention prediction index information, a cell reliability factor, chip position information, program time information, read time information, a process index, or wafer size information. ### Claim 14 (depends on 12) The storage device of claim 12, wherein the storage controller receives the first or second health index information stored in a security block of the respective first non-volatile memory device or second non-volatile memory device, in response to the storage device being powered on and initialized. ### Claim 15 (depends on 12) The storage device of claim 12, wherein a first operation voltage of the first soft erase operation is lower than a second operation voltage of a normal erase operation. ### Claim 16 (depends on 12) The storage device of claim 12, wherein a read level offset of a first temperature region in the first non-volatile memory device is different from a read level offset of a second temperature region in the first non-volatile memory device. ### Claim 17 (depends on 12) The storage device of claim 12, wherein the first non-volatile memory device is on a first chip, and the second non-volatile memory device is on a second chip different from the first chip. ### Claim 18 A storage device comprising: a first non-volatile memory device and a second non-volatile memory device, the first non-volatile memory device including a first normal memory block and a first security block, the first security block storing first health index information, the first health index information including a first on-cell count value extracted from a reference voltage after performing a first soft erase operation on the first non-volatile memory device, and the second non-volatile memory device including a second normal memory block and a second security block, the second security block storing second health index information, the second health index information including a second on-cell count value extracted from a reference voltage after performing a second soft erase operation on the second non-volatile memory device; and a storage controller including processing circuitry configured to, generate and store the first and second health index information by, extracting a respective one of the first or second on-cell count values by performing a respective one of the first or second soft erase operations on the respective one of the first or second non-volatile memory devices, and storing the respective one of the first or second on-cell count values as the first health index information stored in the first non-volatile memory device and the second health index information stored in the second non-volatile memory device, respectively, read data of the first non-volatile memory device by, determining a first read level offset based on a distribution of the first on-cell count values in the first health index information, selecting a first pre-defined read level offset table (PDT) based on the first read level offset, and transmitting a first read command to the first non-volatile memory device based on the first PDT such that the first read command include the first read level offset, and read data of the second non-volatile memory device by, determining a second read level offset based on a distribution of the second on-cell count values in the second health index information, selecting a second pre-defined read level offset table (PDT) based on the second read level offset, and transmitting a second read command to the second non-volatile memory device based on the second PDT such that the second read command include the second read level offset. ### Claim 19 (depends on 18) The storage device of claim 18, wherein the first non-volatile memory device and the second non-volatile memory device are on different chips, and a read level offset set of the first PDT is different from a read level offset set of the second PDT. ### Claim 20 (depends on 18) The storage device of claim 18, wherein a read level offset of a first state of the first PDT has a different value from a read level offset of a second state of the first PDT.