# US 12,190,957 B2 · Dynamic step voltage level adjustment > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,957 B2 - Document ID: US12190957B2 - Status: Granted - Kind: B2 - Application number: 17/939,273 - Filed: 2022-09-07 - Published: 2023-05-04 - Granted: 2025-01-07 - Earliest claimed: 2021-11-02 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Carmine Miccoli; Andrew Bicksler - Web page: https://patentgrep.com/patent/US12190957B2 ## CPC - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/12: Programming voltage switching circuits - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 16/10: Programming or data input circuits - G11C 16/24: Bit-line control circuits - G11C 16/32: Timing circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Processing logic in a memory device receives a request to execute a programming operation on a set of memory cells of the memory device. A first set of programming pulses corresponding to a first step voltage level are caused to be applied to one or more wordlines associated with the set of memory cells. The processing logic determines that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition. A second set of programming pulses corresponding to a second step voltage level is caused to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied. ## Claims ### Claim 1 A memory device comprising: a memory array comprising a set of memory cells; and processing logic, operatively coupled with the memory array, to perform operations comprising: receiving a request to execute a programming operation on the set of memory cells; causing a first set of programming pulses corresponding to a first step voltage level to be applied to one or more wordlines associated with the set of memory cells; determining that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition, wherein the condition is satisfied when the programming voltage level is greater than or equal to a programming voltage threshold level; and causing a second set of programming pulses corresponding to a second step voltage level to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied. ### Claim 2 (depends on 1) The memory device of claim 1, the operations further comprising comparing the programming voltage level associated with the programming pulse to the programming voltage threshold level. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the second step voltage level is less than the first step voltage level. ### Claim 4 (depends on 1) The memory device of claim 1, wherein a respective programming voltage level of each programming pulse in the first set of programming pulses increases by the first step voltage level, and wherein a respective programming voltage of each programming pulse in the second set of programming pulses increases by the second step voltage level, and wherein the second step voltage level is less than the first step voltage level. ### Claim 5 (depends on 1) The memory device of claim 1, wherein each of the first set of programming pulses have a first pulse duration. ### Claim 6 (depends on 5) The memory device of claim 5, the operations further comprising adjusting the first pulse duration to a second pulse duration in response to the condition being satisfied, wherein each of the second set of programming pulses have the second pulse duration. ### Claim 7 (depends on 1) The memory device of claim 1, the operations further comprising: determining that a further programming voltage level associated with a further programming pulse of the second set of programming pulses satisfies an additional condition; and causing a third set of programming pulses corresponding to a third step voltage level to be applied to the one or more wordlines associated with the set of memory cells in response to the additional condition being satisfied. ### Claim 8 A non-transitory computer readable medium comprising instructions, which when executed by a processing device, cause the processing device to perform operations comprising: receiving a request to execute a program operation on a set of memory cells; determining that a programming voltage level associated with a programming pulse of a first set of programming pulses associated with a first step voltage level satisfies a condition, wherein the condition is satisfied when the programming voltage level is greater than or equal to a programming voltage threshold level; and causing a second set of programming pulses corresponding to a second step voltage level to be applied to a wordline associated with the set of memory cells in response to the condition being satisfied. ### Claim 9 (depends on 8) The non-transitory computer readable medium of claim 8, wherein the second step voltage level is less than the first step voltage level. ### Claim 10 (depends on 8) The non-transitory computer readable medium of claim 8, wherein each of the first set of programming pulses have a first pulse duration. ### Claim 11 (depends on 10) The non-transitory computer readable medium of claim 10, the operations further comprising adjusting the first pulse duration to a second pulse duration in response to the condition being satisfied, wherein each of the second set of programming pulses have the second pulse duration. ### Claim 12 (depends on 9) The non-transitory computer readable medium of claim 9, wherein the second step voltage level is used to establish programming voltage levels of the second set of programming pulses in response to the first condition being satisfied. ### Claim 13 (depends on 9) The non-transitory computer readable medium of claim 9, the operations further comprising causing a third set of programming pulses corresponding to a third step voltage level to be applied the wordline. ### Claim 14 A method comprising: receiving, by a processing device, a request to execute a programming operation on a set of memory cells; causing a first set of programming pulses corresponding to a first step voltage level to be applied to one or more wordlines associated with the set of memory cells; determining that a programming voltage level associated with a programming pulse of the first set of programming pulses satisfies a condition, wherein the condition is satisfied when the programming voltage level is greater than or equal to a programming voltage threshold level; and causing a second set of programming pulses corresponding to a second step voltage level to be applied to the one or more wordlines associated with the set of memory cells in response to the condition being satisfied. ### Claim 15 (depends on 14) The method of claim 14, further comprising comparing the programming voltage level associated with the programming pulse to the programming voltage threshold level. ### Claim 16 (depends on 14) The method of claim 14, wherein the second step voltage level is less than the first step voltage level. ### Claim 17 (depends on 14) The method of claim 14, wherein each of the first set of programming pulses have a first pulse duration. ### Claim 18 (depends on 17) The method of claim 17, further comprising adjusting the first pulse duration to a second pulse duration in response to the condition being satisfied, wherein each of the second set of programming pulses have the second pulse duration. ### Claim 19 (depends on 14) The method of claim 14, further comprising: determining that a further programming voltage level associated with a further programming pulse of the second set of programming pulses satisfies an additional condition; and causing a third set of programming pulses corresponding to a third step voltage level to be applied to the one or more wordlines associated with the set of memory cells in response to the additional condition being satisfied.