# US 12,190,955 B2 · Memory device with dummy word line, system and method for programming thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,190,955 B2 - Document ID: US12190955B2 - Status: Granted - Kind: B2 - Application number: 17/881,231 - Filed: 2022-08-04 - Published: 2023-01-26 - Granted: 2025-01-07 - Earliest claimed: 2021-06-25 - Assignees: Yangtze Memory Technologies Co., Ltd. - Applicants: Yangtze Memory Technologies Co., Ltd. - Inventors: Xueqing Huang; Wei Huang; Xing Zhou; Chan Wang; Kang Li; Cong Luo; Fengxiang Gao - Web page: https://patentgrep.com/patent/US12190955B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C 7/14: Dummy cell management; Sense reference voltage generators - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 16/32: Timing circuits - G11C 16/3427: {Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device includes a memory cell array including memory blocks and a peripheral circuit coupled to the memory cell array. Each memory block includes memory strings each including dummy cells and select transistors, bit lines coupled to the memory strings, select lines including first select lines and second select lines, and one or more dummy word lines. Each select line coupled to the select transistors. The first select lines are closer to the bit lines than the second select lines. Each dummy word line is coupled to the respective dummy cells. The dummy word lines include a first dummy word line adjacent to either the first select lines or the second select lines. The peripheral circuit is configured to apply a turn-on voltage to all the first select lines, and apply a program voltage to the first dummy word line. ## Claims ### Claim 1 A memory device, comprising: a memory cell array comprising memory blocks, each memory block comprising: memory strings, each memory string comprising dummy cells and select transistors; bit lines coupled to the memory strings; select lines, each select line coupled to the select transistors; and one or more dummy word lines, each dummy word line coupled to the respective dummy cells, wherein the memory blocks comprise a first memory block, the selected lines in the first memory block comprises one or more first select lines and one or more second select lines, the one or more first select lines are closer to the bit lines than the one or more second select lines, the one or more dummy word lines in the first memory block comprises a first dummy word line adjacent to either the one or more first select lines or the one or more second select lines, and a second dummy word line, wherein the one or more dummy word lines are between the one or more first select lines and the one or more second select lines; and a peripheral circuit coupled to the memory cell array, configured to: apply a turn-on voltage to the one or more first select lines in the first memory block during a first time period; apply a bias voltage to the second dummy word line during a second time period; and apply a program voltage to the first dummy word line during a third time period, wherein the first time period comprises the third time period, and the second time period comprises the third time period. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first dummy word line is adjacent to the one or more first select lines. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the peripheral circuit is further configured to: apply a turn-off voltage to one or more second select lines at least during the second time period. ### Claim 4 (depends on 1) The memory device of claim 1, wherein the first dummy word line is adjacent to the one or more second select lines. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the bias voltage is less than the program voltage. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the peripheral circuit is further configured to: apply the bias voltage to the first dummy word line during a fourth time period, wherein the second time period comprises the fourth time period. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the peripheral circuit is further configured to: apply a ground voltage to the bit lines during a fifth time period, wherein the fifth time period comprises the second time period. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the peripheral circuit is further configured to: apply a precharge voltage to the bit lines during a sixth time period, wherein the sixth time period is before the third time period. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the peripheral circuit is further configured to: apply the turn-on voltage to the one or more first select lines during a seventh time period, wherein the seventh time period comprises the sixth time period. ### Claim 10 (depends on 1) The memory device of claim 1, wherein the select transistors comprises: first select transistors located at the same height distant from a common source line, wherein gate terminals of the first select transistors in each of the memory strings are coupled to the corresponding one or more first select lines; and second select transistors located at the same height distant from the common source line, wherein gate terminals of the second select transistors in each of the memory strings are coupled to one of the one or more second select lines. ### Claim 11 (depends on 1) The memory device of claim 1, wherein the program voltage is greater than the turn-on voltage. ### Claim 12 A memory system, comprising: a memory device comprising: a memory cell array comprising memory blocks, each memory block comprising: memory strings, each memory string comprising dummy cells and select transistors; bit lines coupled to the memory strings; one or more select lines, each select line coupled to the select transistors; and one or more dummy word lines, each dummy word line coupled to the respective dummy cells, wherein the memory blocks comprise a first memory block, the selected lines in the first memory block comprises one or more first select lines and one or more second select lines, and the one or more dummy word lines in the first memory block comprises a first dummy word line adjacent to either the one or more first select lines or the one or more second select lines, and a second dummy word line, wherein the one or more first select lines are closer to the bit lines than the one or more second select lines, wherein the one or more dummy word lines are between the one or more first select lines and the one or more second select lines; and a peripheral circuit coupled to the memory cell array, configured to: apply a turn-on voltage to the one or more first select lines in the first memory block during a first time period; apply a bias voltage to the second dummy word line during a second time period; and apply a program voltage to the first dummy word line during a third time period, wherein the first time period comprises the third time period, and the second time period comprises the third time period; and a memory controller coupled to the memory device and configured to control the memory device. ### Claim 13 (depends on 12) The memory system of claim 12, wherein the first dummy word line is adjacent to the one or more first select lines. ### Claim 14 (depends on 13) The memory system of claim 13, wherein the peripheral circuit is further configured to: apply a turn-off voltage to the one or more second select lines at least during the second time period. ### Claim 15 (depends on 12) The memory system of claim 12, wherein the first dummy word line is adjacent to the one or more second select lines. ### Claim 16 A method for programming a memory device, the memory device comprising a memory cell array comprising memory blocks, each memory block comprising: (i) memory strings, each memory string comprising dummy cells and select transistors, (ii) bit lines coupled to the memory strings, (iii) select lines, each select line being coupled to the select transistors, and (iv) one or more dummy word lines, each dummy word line being coupled to the respective dummy cells, wherein the memory blocks comprise a first memory block, the selected lines in the first memory block comprises one or more first select lines and one or more second select lines, and the dummy word lines in the first memory block comprises a first dummy word line adjacent to either the one or more first select lines or the one or more second select lines, and a second dummy word line, wherein the one or more first select lines are closer to the bit lines than the one or more second select lines, wherein the one or more dummy word lines are between the one or more first select lines and the one or more second select lines, wherein the method comprises: applying a turn-on voltage to the one or more first select lines in the first memory block during a first time period; applying a bias voltage to the second dummy word line during a second time period; and applying a program voltage to the first dummy word line during a third time period, wherein the first time period comprises the third time period, and the second time period comprises the third time period. ### Claim 17 (depends on 16) The method of claim 16, wherein the first dummy word line is adjacent to the one or more first select lines. ### Claim 18 (depends on 17) The method of claim 17, further comprising: applying a turn-off voltage to the one or more second select lines at least during the second time period. ### Claim 19 (depends on 16) The method of claim 16, wherein the first dummy word line is adjacent to the one or more second select lines. ### Claim 20 (depends on 16) The method of claim 16, wherein the bias voltage is less than the program voltage.